Skip to content
View mahammadali4's full-sized avatar

Block or report mahammadali4

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Spike-based, VHDL, generic TDE model on FPGA for neuromorphic sensors

VHDL 5 Updated Dec 9, 2021

Brilliantly Radical Artificially Intelligent Neural Machine

Verilog 16 2 Updated Dec 28, 2017

A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.

Verilog 41 6 Updated Feb 18, 2024

The Antikernel operating system project

Verilog 115 10 Updated Apr 23, 2020

RISC-V 32-bit microcontroller developed in Verilog

Verilog 165 21 Updated Oct 21, 2024
Verilog 78 34 Updated Dec 24, 2024

The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researchers under the supervision of Prof: Manan Suri (NVM &Neuromorp…

Verilog 9 1 Updated Jan 6, 2023

tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.

Verilog 49 10 Updated Mar 30, 2023

FPGA implementation of Izhikevich Neuron Model.

Verilog 4 Updated Nov 7, 2023

Fully opensource spiking neural network accelerator

Verilog 134 16 Updated Feb 13, 2023

[FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.

C++ 53 5 Updated Jul 28, 2021

A repository FPGA-friendly SNN models

Python 32 6 Updated Mar 24, 2021

Deep and online learning with spiking neural networks in Python

Python 1,428 246 Updated Aug 7, 2024

Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )

SystemVerilog 54 5 Updated Nov 7, 2024

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

Verilog 149 32 Updated Mar 26, 2022

FPGA Design of a Spiking Neural Network.

VHDL 35 6 Updated May 15, 2024

RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine

Verilog 22 8 Updated Mar 17, 2022

Open-Source Network-on-Chip for European Projects activities

Verilog 1 Updated Sep 11, 2024

On-Chip Spike Detection and Classification using Neural Networks and Approximate Computing

Verilog 2 Updated Nov 30, 2023

Implementation of Serpent symmetrical cryptoalgorithm as Network on Chip

Verilog 1 Updated Sep 29, 2023

My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA

Verilog 12 1 Updated Jun 26, 2018

Synthesize and P&R an Network-on-Chip Router

Verilog 5 2 Updated Dec 6, 2019

Router for Network-on-Chip (NoC) with Virtual Channels (VC) from Netmaker library, modified for synthesis in Quartus II

Verilog 7 4 Updated Oct 29, 2013

Simulation, synthesis, and physical design for an NoC. Each tile of the chip multiprocessor (CMP) NoC has a router and associated processing core.

Verilog 5 1 Updated Nov 21, 2020

A verilog implementation for Network-on-Chip

Verilog 71 21 Updated Feb 3, 2018

Efficient Spiking Neural Network framework, built on top of PyTorch for GPU acceleration

Python 222 27 Updated Jul 31, 2024
Python 98 17 Updated Nov 25, 2020

Spiking Neural Networks in C++ with strong GPU acceleration through CUDA

Cuda 125 24 Updated Jul 3, 2020
Next