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Merge tag 'powerpc-4.2-1' of git://git.kernel.org/pub/scm/linux/kerne…
…l/git/mpe/linux Pull powerpc updates from Michael Ellerman: - disable the 32-bit vdso when building LE, so we can build with a 64-bit only toolchain. - EEH fixes from Gavin & Richard. - enable the sys_kcmp syscall from Laurent. - sysfs control for fastsleep workaround from Shreyas. - expose OPAL events as an irq chip by Alistair. - MSI ops moved to pci_controller_ops by Daniel. - fix for kernel to userspace backtraces for perf from Anton. - merge pseries and pseries_le defconfigs from Cyril. - CXL in-kernel API from Mikey. - OPAL prd driver from Jeremy. - fix for DSCR handling & tests from Anshuman. - Powernv flash mtd driver from Cyril. - dynamic DMA Window support on powernv from Alexey. - LLVM clang fixes & workarounds from Anton. - reworked version of the patch to abort syscalls when transactional. - fix the swap encoding to support 4TB, from Aneesh. - various fixes as usual. - Freescale updates from Scott: Highlights include more 8xx optimizations, an e6500 hugetlb optimization, QMan device tree nodes, t1024/t1023 support, and various fixes and cleanup. * tag 'powerpc-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux: (180 commits) cxl: Fix typo in debug print cxl: Add CXL_KERNEL_API config option powerpc/powernv: Fix wrong IOMMU table in pnv_ioda_setup_bus_dma() powerpc/mm: Change the swap encoding in pte. powerpc/mm: PTE_RPN_MAX is not used, remove the same powerpc/tm: Abort syscalls in active transactions powerpc/iommu/ioda2: Enable compile with IOV=on and IOMMU_API=off powerpc/include: Add opal-prd to installed uapi headers powerpc/powernv: fix construction of opal PRD messages powerpc/powernv: Increase opal-irqchip initcall priority powerpc: Make doorbell check preemption safe powerpc/powernv: pnv_init_idle_states() should only run on powernv macintosh/nvram: Remove as unused powerpc: Don't use gcc specific options on clang powerpc: Don't use -mno-strict-align on clang powerpc: Only use -mtraceback=no, -mno-string and -msoft-float if toolchain supports it powerpc: Only use -mabi=altivec if toolchain supports it powerpc: Fix duplicate const clang warning in user access code vfio: powerpc/spapr: Support Dynamic DMA windows vfio: powerpc/spapr: Register memory and define IOMMU v2 ...
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@@ -6,6 +6,17 @@ Example: The real path of the attribute /sys/class/cxl/afu0.0s/irqs_max is | |
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| Slave contexts (eg. /sys/class/cxl/afu0.0s): | ||
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| What: /sys/class/cxl/<afu>/afu_err_buf | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| AFU Error Buffer contents. The contents of this file are | ||
| application specific and depends on the AFU being used. | ||
| Applications interacting with the AFU can use this attribute | ||
| to know about the current error condition and take appropriate | ||
| action like logging the event etc. | ||
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| What: /sys/class/cxl/<afu>/irqs_max | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
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@@ -15,6 +26,7 @@ Description: read/write | |
| that hardware can support (eg. 2037). Write values will limit | ||
| userspace applications to that many userspace interrupts. Must | ||
| be >= irqs_min. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/irqs_min | ||
| Date: September 2014 | ||
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@@ -24,20 +36,23 @@ Description: read only | |
| userspace must request on a CXL_START_WORK ioctl. Userspace may | ||
| omit the num_interrupts field in the START_WORK IOCTL to get | ||
| this minimum automatically. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/mmio_size | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| Decimal value of the size of the MMIO space that may be mmaped | ||
| by userspace. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/modes_supported | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| List of the modes this AFU supports. One per line. | ||
| Valid entries are: "dedicated_process" and "afu_directed" | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/mode | ||
| Date: September 2014 | ||
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@@ -46,6 +61,7 @@ Description: read/write | |
| The current mode the AFU is using. Will be one of the modes | ||
| given in modes_supported. Writing will change the mode | ||
| provided that no user contexts are attached. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/prefault_mode | ||
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@@ -59,26 +75,30 @@ Description: read/write | |
| descriptor as an effective address and | ||
| prefault what it points to. | ||
| all: all segments process calling START_WORK maps. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/reset | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
| Description: write only | ||
| Writing 1 here will reset the AFU provided there are not | ||
| contexts active on the AFU. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/api_version | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| Decimal value of the current version of the kernel/user API. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/api_version_compatible | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| Decimal value of the the lowest version of the userspace API | ||
| this this kernel supports. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| AFU configuration records (eg. /sys/class/cxl/afu0.0/cr0): | ||
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@@ -92,20 +112,23 @@ Contact: [email protected] | |
| Description: read only | ||
| Hexadecimal value of the vendor ID found in this AFU | ||
| configuration record. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/cr<config num>/device | ||
| Date: February 2015 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| Hexadecimal value of the device ID found in this AFU | ||
| configuration record. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/cr<config num>/class | ||
| Date: February 2015 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| Hexadecimal value of the class code found in this AFU | ||
| configuration record. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>/cr<config num>/config | ||
| Date: February 2015 | ||
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@@ -115,6 +138,7 @@ Description: read only | |
| record. The format is expected to match the either the standard | ||
| or extended configuration space defined by the PCIe | ||
| specification. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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@@ -126,18 +150,21 @@ Contact: [email protected] | |
| Description: read only | ||
| Decimal value of the size of the MMIO space that may be mmaped | ||
| by userspace. This includes all slave contexts space also. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>m/pp_mmio_len | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| Decimal value of the Per Process MMIO space length. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<afu>m/pp_mmio_off | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| Decimal value of the Per Process MMIO space offset. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| Card info (eg. /sys/class/cxl/card0) | ||
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@@ -147,12 +174,14 @@ Date: September 2014 | |
| Contact: [email protected] | ||
| Description: read only | ||
| Identifies the CAIA Version the card implements. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<card>/psl_revision | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| Identifies the revision level of the PSL. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<card>/base_image | ||
| Date: September 2014 | ||
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@@ -162,13 +191,15 @@ Description: read only | |
| that support loadable PSLs. For FPGAs this field identifies | ||
| the image contained in the on-adapter flash which is loaded | ||
| during the initial program load. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<card>/image_loaded | ||
| Date: September 2014 | ||
| Contact: [email protected] | ||
| Description: read only | ||
| Will return "user" or "factory" depending on the image loaded | ||
| onto the card. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<card>/load_image_on_perst | ||
| Date: December 2014 | ||
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@@ -183,10 +214,12 @@ Description: read/write | |
| user or factory image to be loaded. | ||
| Default is to reload on PERST whichever image the card has | ||
| loaded. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| What: /sys/class/cxl/<card>/reset | ||
| Date: October 2014 | ||
| Contact: [email protected] | ||
| Description: write only | ||
| Writing 1 will issue a PERST to card which may cause the card | ||
| to reload the FPGA depending on load_image_on_perst. | ||
| Users: https://github.com/ibm-capi/libcxl | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,83 @@ | ||
| DSCR (Data Stream Control Register) | ||
| ================================================ | ||
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| DSCR register in powerpc allows user to have some control of prefetch of data | ||
| stream in the processor. Please refer to the ISA documents or related manual | ||
| for more detailed information regarding how to use this DSCR to attain this | ||
| control of the pefetches . This document here provides an overview of kernel | ||
| support for DSCR, related kernel objects, it's functionalities and exported | ||
| user interface. | ||
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| (A) Data Structures: | ||
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| (1) thread_struct: | ||
| dscr /* Thread DSCR value */ | ||
| dscr_inherit /* Thread has changed default DSCR */ | ||
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| (2) PACA: | ||
| dscr_default /* per-CPU DSCR default value */ | ||
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| (3) sysfs.c: | ||
| dscr_default /* System DSCR default value */ | ||
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| (B) Scheduler Changes: | ||
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| Scheduler will write the per-CPU DSCR default which is stored in the | ||
| CPU's PACA value into the register if the thread has dscr_inherit value | ||
| cleared which means that it has not changed the default DSCR till now. | ||
| If the dscr_inherit value is set which means that it has changed the | ||
| default DSCR value, scheduler will write the changed value which will | ||
| now be contained in thread struct's dscr into the register instead of | ||
| the per-CPU default PACA based DSCR value. | ||
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| NOTE: Please note here that the system wide global DSCR value never | ||
| gets used directly in the scheduler process context switch at all. | ||
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| (C) SYSFS Interface: | ||
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| Global DSCR default: /sys/devices/system/cpu/dscr_default | ||
| CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr | ||
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| Changing the global DSCR default in the sysfs will change all the CPU | ||
| specific DSCR defaults immediately in their PACA structures. Again if | ||
| the current process has the dscr_inherit clear, it also writes the new | ||
| value into every CPU's DSCR register right away and updates the current | ||
| thread's DSCR value as well. | ||
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| Changing the CPU specif DSCR default value in the sysfs does exactly | ||
| the same thing as above but unlike the global one above, it just changes | ||
| stuff for that particular CPU instead for all the CPUs on the system. | ||
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| (D) User Space Instructions: | ||
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| The DSCR register can be accessed in the user space using any of these | ||
| two SPR numbers available for that purpose. | ||
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| (1) Problem state SPR: 0x03 (Un-privileged, POWER8 only) | ||
| (2) Privileged state SPR: 0x11 (Privileged) | ||
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| Accessing DSCR through privileged SPR number (0x11) from user space | ||
| works, as it is emulated following an illegal instruction exception | ||
| inside the kernel. Both mfspr and mtspr instructions are emulated. | ||
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| Accessing DSCR through user level SPR (0x03) from user space will first | ||
| create a facility unavailable exception. Inside this exception handler | ||
| all mfspr isntruction based read attempts will get emulated and returned | ||
| where as the first mtspr instruction based write attempts will enable | ||
| the DSCR facility for the next time around (both for read and write) by | ||
| setting DSCR facility in the FSCR register. | ||
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| (E) Specifics about 'dscr_inherit': | ||
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| The thread struct element 'dscr_inherit' represents whether the thread | ||
| in question has attempted and changed the DSCR itself using any of the | ||
| following methods. This element signifies whether the thread wants to | ||
| use the CPU default DSCR value or its own changed DSCR value in the | ||
| kernel. | ||
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| (1) mtspr instruction (SPR number 0x03) | ||
| (2) mtspr instruction (SPR number 0x11) | ||
| (3) ptrace interface (Explicitly set user DSCR value) | ||
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| Any child of the process created after this event in the process inherits | ||
| this same behaviour as well. |
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