drm/i915/cnl: Fix PLL mapping.

On PLL Enable sequence we need to "Configure DPCLKA_CFGCR0 to turn on
the clock for the DDI and map the DPLL to the DDI"

So we first do the map and then we unset DDI_CLK_OFF to turn the clock
on. We do this in 2 separated steps.

However, on this second step where we should only unset the off bit we are
also unmapping the ddi from the pll. So we end up using the pll 0
for almost everything. Consequently breaking cases with more than one
display.

Fixes: 555e38d ("drm/i915/cnl: DDI - PLL mapping")
Cc: Paulo Zanoni <[email protected]>
Cc: Manasi Navare <[email protected]>
Cc: Kahola, Mika <[email protected]>
Signed-off-by: Rodrigo Vivi <[email protected]>
Reviewed-by: James Ausmus <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit 87145d9)
Signed-off-by: Rodrigo Vivi <[email protected]>

drivers/gpu/drm/i915/intel_ddi.c

@@ -2102,8 +2102,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 		 * register writes.
 		 */
 		val = I915_READ(DPCLKA_CFGCR0);
-		val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
-			 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
 		I915_WRITE(DPCLKA_CFGCR0, val);
 	} else if (IS_GEN9_BC(dev_priv)) {
 		/* DDI -> PLL mapping  */