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EDAC, mce_amd: Rename nb_bus_decoder to dram_ecc_decoder
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nb_bus_decoder() is only used for DRAM ECC errors so rename it so that
the name is more generic and descriptive.

Also, call it for DRAM ECC errors on SMCA systems.

[ Boris: rename it to real function name with a verb in it. ]

Signed-off-by: Yazen Ghannam <[email protected]>
Cc: Aravind Gopalakrishnan <[email protected]>
Cc: linux-edac <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Borislav Petkov <[email protected]>
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yghannam authored and suryasaimadhu committed Nov 21, 2016
1 parent 1e8096b commit 5c33220
Showing 1 changed file with 14 additions and 7 deletions.
21 changes: 14 additions & 7 deletions drivers/edac/mce_amd.c
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ static struct amd_decoder_ops *fam_ops;
static u8 xec_mask = 0xf;

static bool report_gart_errors;
static void (*nb_bus_decoder)(int node_id, struct mce *m);
static void (*decode_dram_ecc)(int node_id, struct mce *m);

void amd_report_gart_errors(bool v)
{
Expand All @@ -18,16 +18,16 @@ EXPORT_SYMBOL_GPL(amd_report_gart_errors);

void amd_register_ecc_decoder(void (*f)(int, struct mce *))
{
nb_bus_decoder = f;
decode_dram_ecc = f;
}
EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);

void amd_unregister_ecc_decoder(void (*f)(int, struct mce *))
{
if (nb_bus_decoder) {
WARN_ON(nb_bus_decoder != f);
if (decode_dram_ecc) {
WARN_ON(decode_dram_ecc != f);

nb_bus_decoder = NULL;
decode_dram_ecc = NULL;
}
}
EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
Expand Down Expand Up @@ -763,8 +763,8 @@ static void decode_mc4_mce(struct mce *m)

pr_cont("%s.\n", mc4_mce_desc[xec]);

if (nb_bus_decoder)
nb_bus_decoder(node_id, m);
if (decode_dram_ecc)
decode_dram_ecc(node_id, m);
return;
}
break;
Expand Down Expand Up @@ -877,6 +877,13 @@ static void decode_smca_errors(struct mce *m)
pr_emerg(HW_ERR "%s Error: ", ip_name);
pr_cont("%s.\n", smca_mce_descs[bank_type].descs[xec]);
}

/*
* amd_get_nb_id() returns the last level cache id.
* The last level cache on Fam17h is 1 level below the node.
*/
if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc)
decode_dram_ecc(amd_get_nb_id(m->extcpu) >> 1, m);
}

static inline void amd_decode_err_code(u16 ec)
Expand Down

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