board: cssi: Add CPU board CMPCPRO

CSSI has another CPU board, similar to the CMPC885 board that get plugged on the two base boards MCR3000_2G and MIAE. That CPU board is called CMPCPRO because it has a MPC8321E CPU, also known as Power QUICC II PRO. Signed-off-by: Christophe Leroy <[email protected]>
matwey · Apr 28, 2023 · 4d0c8db · 4d0c8db
1 parent 78ba7b6
commit 4d0c8db
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diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -20,6 +20,10 @@ choice
 	prompt "Target select"
 	optional
 
+config TARGET_CMPCPRO
+	bool "Support CMPCPRO board from CSSI"
+	select ARCH_MPC832X
+
 config TARGET_MPC837XERDB
 	bool "Support MPC837XERDB"
 	select ARCH_MPC837X
@@ -205,5 +209,6 @@ config NEVER_ASSERT_ODT_TO_CPU
 
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/gdsys/mpc8308/Kconfig"
+source "board/cssi/cmpcpro/Kconfig"
 
 endmenu
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb
 dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
 dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
 dtb-$(CONFIG_TARGET_CMPC885) += cmpc885.dtb
+dtb-$(CONFIG_TARGET_CMPCPRO) += cmpcpro.dtb
 
 include $(srctree)/scripts/Makefile.dts
 

diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CMPC885 Device Tree Source
+ *
+ * Copyright 2020 CS GROUP France
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/clk/mpc83xx-clk.h>
+
+/ {
+	model = "CMPCPRO";
+	compatible = "fsl, cmpc85xx", "fsl,mod85xx", "CMPCPRO", "MPC8321E", "fsl,cmpcpro";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		stdout-path = &serial0;
+	};
+	WDT: watchdog@0 {
+		device_type = "watchdog";
+		compatible = "fsl,pq1-wdt";
+	};
+
+	aliases {
+		ethernet0 = &eth0;
+		etehrnet1 = &eth1;
+		serial0 = &serial0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		PowerPC,8321@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			d-cache-line-size = <0x20>;	// 32 bytes
+			i-cache-line-size = <0x20>;	// 32 bytes
+			d-cache-size = <16384>;	// L1, 16K
+			i-cache-size = <16384>;	// L1, 16K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	soc8321@b0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+		ranges = <0x0 0xb0000000 0x00100000>;
+		reg = <0xb0000000 0x00000200>;
+		bus-frequency = <0>;
+		pmc: power@b00 {
+			compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
+			reg = <0xb00 0x100 0xa00 0x100>;
+			interrupts = <80 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+		serial0: serial@4500 {
+			clocks = <&socclocks MPC83XX_CLK_CSB>;
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <0>;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+		ipic:pic@700 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <0x700 0x100>;
+			device_type = "ipic";
+		};
+		par_io@1400 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x1400 0x100>;
+			ranges;
+			compatible = "fsl,mpc8323-qe-pario","simple-bus";
+			device_type = "par_io";
+			num-ports = <7>;
+			qe_pio_a: gpio-controller@1400 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+				reg = <0x1400 0x18>;
+				gpio-controller;
+			};
+			qe_pio_b: gpio-controller@1418 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+				reg = <0x1418 0x18>;
+				gpio-controller;
+			};
+			qe_pio_c: gpio-controller@1430 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+				reg = <0x1430 0x18>;
+				gpio-controller;
+			};
+			qe_pio_d: gpio-controller@1448 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+				reg = <0x1448 0x18>;
+				gpio-controller;
+			};
+		};
+	};
+	socclocks: clocks {
+		bootph-all;
+		compatible = "fsl,mpc832x-clk";
+		#clock-cells = <1>;
+	};
+	qe@b0100000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "qe";
+		compatible = "fsl,qe","simple-bus";
+		ranges = <0x0 0xb0100000 0x00100000>;
+		reg = <0xb0100000 0x480>;
+		brg-frequency = <0>;
+		bus-frequency = <198000000>;
+		fsl,qe-num-riscs = <1>;
+		fsl,qe-num-snums = <28>;
+		spi@4c0 {
+			clocks = <&socclocks MPC83XX_CLK_CSB>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc832x-spi";
+			reg = <0x4c0 0x40>;
+			mode = "cpu";
+			gpios = <&qe_pio_d 3 1>;
+			clock-frequency = <0>;
+			eeprom@3 {
+				compatible = "atmel,at25", "cs,eeprom";
+				cell-index = <1>;
+			};
+		};
+		eth0: ucc@3000 {
+			device_type = "network";
+			compatible = "ucc_geth";
+			cell-index = <2>;
+			reg = <0x3000 0x200>;
+			rx-clock-name = "clk17";
+			tx-clock-name = "clk17";
+			phy-handle = <&phy1>;
+			phy-connection-type = "rmii";
+		};
+		eth1: ucc@2200 {
+			device_type = "network";
+			compatible = "ucc_geth";
+			cell-index = <3>;
+			reg = <0x2200 0x200>;
+			rx-clock-name = "clk12";
+			tx-clock-name = "clk12";
+			phy-handle = <&phy2>;
+			phy-connection-type = "rmii";
+		};
+		mdio@3120 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3120 0x18>;
+			compatible = "fsl,ucc-mdio";
+			phy1:ethernet-phy@1 {
+				interrupt-parent = <&ipic>;
+				reg = <0x1>;
+				interrupts = <17 8>;
+				device_type = "ethernet-phy";
+			};
+			phy2:ethernet-phy@2 {
+				interrupt-parent = <&ipic>;
+				reg = <0x2>;
+				interrupts = <17 8>;
+				device_type = "ethernet-phy";
+			};
+		};
+	};
+};
diff --git a/board/cssi/MAINTAINERS b/board/cssi/MAINTAINERS
@@ -6,3 +6,5 @@ F:	include/configs/mcr3000.h
 F:	configs/MCR3000_defconfig
 F:	include/configs/cmpc885.h
 F:	configs/CMPC885_defconfig
+F:	include/configs/cmpcpro.h
+F:	configs/CMPCPRO_defconfig
diff --git a/board/cssi/cmpcpro/Kconfig b/board/cssi/cmpcpro/Kconfig
@@ -0,0 +1,26 @@
+if TARGET_CMPCPRO
+
+config SYS_BOARD
+	default "cmpcpro"
+
+config SYS_VENDOR
+	default "cssi"
+
+config SYS_CONFIG_NAME
+	default "cmpcpro"
+
+config TEXT_BASE
+	default 0x40000000
+
+config CPLD_BASE
+	hex
+	default 0x90000000
+
+config FPGA_BASE
+	hex
+	default 0x80000000
+
+config PCI
+	default no
+
+endif
diff --git a/board/cssi/cmpcpro/Makefile b/board/cssi/cmpcpro/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, [email protected].
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cmpcpro.o nand.o ../common/common.o