Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig

This converts the following to Kconfig: CONFIG_SYS_DDR_RAW_TIMING Signed-off-by: Tom Rini <[email protected]>
matwey · Jul 5, 2022 · c24e8e2 · c24e8e2
1 parent bca4509
commit c24e8e2
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Showing 55 changed files with 54 additions and 18 deletions.
diff --git a/README b/README
@@ -2079,12 +2079,6 @@ Low Level (hardware related) configuration options:
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
 
-- CONFIG_SYS_DDR_RAW_TIMING
-		Get DDR timing information from other than SPD. Common with
-		soldered DDR chips onboard without SPD. DDR raw timing
-		parameters are extracted from datasheet and hard-coded into
-		header files or board specific files.
-
 - CONFIG_FSL_DDR_INTERACTIVE
 		Enable interactive DDR debugging. See doc/README.fsl-ddr.
 

diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -82,6 +82,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y

diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -71,6 +71,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -74,6 +74,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
@@ -81,6 +81,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
@@ -48,6 +48,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y

diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -70,6 +70,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -73,6 +73,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -83,6 +83,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -50,6 +50,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y

diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -72,6 +72,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -75,6 +75,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
@@ -82,6 +82,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
@@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y

diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -71,6 +71,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -74,6 +74,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -80,6 +80,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396

diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -70,6 +70,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -73,6 +73,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
@@ -49,6 +49,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
@@ -79,6 +79,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396

diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -69,6 +69,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -72,6 +72,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
@@ -48,6 +48,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
@@ -82,6 +82,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8796

diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -72,6 +72,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -75,6 +75,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
@@ -51,6 +51,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -84,6 +84,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396

diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -74,6 +74,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -77,6 +77,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
@@ -53,6 +53,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
@@ -83,6 +83,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396

diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -73,6 +73,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -76,6 +76,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
@@ -52,6 +52,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7

diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
@@ -95,6 +95,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -62,6 +62,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
@@ -65,6 +65,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -65,6 +65,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
@@ -62,6 +62,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -93,6 +93,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -89,6 +89,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -45,6 +45,7 @@ CONFIG_ETHPRIME="FM1@DTSEC3"
 CONFIG_DM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
@@ -49,6 +49,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -44,6 +44,7 @@ CONFIG_ETHPRIME="FM1@DTSEC3"
 CONFIG_DM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y

diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
@@ -51,6 +51,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y