GitHub - mehaltalukder/UART_UVM_Project: Verification of UART design using UVM (Universal Verification Methodology) and SystemVerilog

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Verification of UART design using UVM (Universal Verification Methodology) and SystemVerilog

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Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
RTL		RTL
UVM_tb		UVM_tb
README.txt		README.txt
run_uart.do		run_uart.do
run_uart.f		run_uart.f

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* This is a project to verify a simple UART design using UVM (Universal Verification Methodology) and SystemVerilog. 
* To run the simulation using a simulator like Questa just run the "run_uart.do" file in the simulator using the following command
- do run_uart.do
* You can also compile and run the files using any other simulator at edaplayground