Update paths for vendored DV code

This commit amends some paths in the vendoring hjson file (and updates config files to use things at the new paths). Finally it re-runs the vendoring tool: Update code from upstream repository https://github.com/lowRISC/opentitan to revision 92e9242424c72c59008e267dd3779e2af5ec8e83 which just ends up with a load of file renames. Signed-off-by: Rupert Swarbrick <[email protected]>
mithro · Nov 28, 2020 · 690f8af · 690f8af
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diff --git a/doc/03_reference/verification.rst b/doc/03_reference/verification.rst
@@ -51,7 +51,7 @@ Memory Model
 """"""""""""
 
 The code is vendored from OpenTitan and can be found in the
-`vendor/lowrisc_ip/mem_model <https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/mem_model>`_
+`vendor/lowrisc_ip/dv/sv/mem_model <https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/dv/sv/mem_model>`_
 directory.
 The testbench instantiates a single instance of this memory model that it loads the compiled
 assembly test program into at the beginning of each test.
@@ -253,7 +253,7 @@ the Ibex repository:
 
 .. code-block:: bash
 
-   ./vendor/lowrisc_ip/dvsim/dvsim.py dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson --build-only
+   ./vendor/lowrisc_ip/util/dvsim/dvsim.py dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson --build-only
    --skip-ral --purge --sr sim_out
 
 Specify the intended output directory using either the ``--sr`` or ``-scratch-root`` option.

diff --git a/dv/uvm/core_ibex/ibex_dv.f b/dv/uvm/core_ibex/ibex_dv.f
@@ -9,23 +9,23 @@
 +define+RVFI
 
 // Shared lowRISC code
-+incdir+${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_assert.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_lfsr.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_28_22_enc.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_28_22_dec.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_39_32_enc.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_39_32_dec.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_72_64_enc.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim/rtl/prim_secded_72_64_dec.sv
++incdir+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_enc.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_dec.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_enc.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_dec.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_enc.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_dec.sv
 
 // Until this list is generated by FuseSoC, we have to use manually generated
 // wrappers around the prim_* modules to instantiate the prim_generic_* ones,
 // see https://github.com/lowRISC/ibex/issues/893.
 ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_pkg.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_ram_1p.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1p.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_ram_1p.sv
-${PRJ_DIR}/vendor/lowrisc_ip/prim_generic/rtl/prim_generic_clock_gating.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_clock_gating.sv
 
 // ibex CORE RTL files
@@ -65,13 +65,13 @@
 +incdir+${PRJ_DIR}/dv/uvm/core_ibex/tests
 +incdir+${PRJ_DIR}/dv/uvm/core_ibex/common/ibex_mem_intf_agent
 +incdir+${PRJ_DIR}/dv/uvm/core_ibex/common/irq_agent
-+incdir+${PRJ_DIR}/vendor/lowrisc_ip/mem_model
-+incdir+${PRJ_DIR}/vendor/lowrisc_ip/dv_utils
++incdir+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/mem_model
++incdir+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/dv_utils
 ${PRJ_DIR}/dv/uvm/bus_params_pkg/bus_params_pkg.sv
-${PRJ_DIR}/vendor/lowrisc_ip/common_ifs/clk_rst_if.sv
-${PRJ_DIR}/vendor/lowrisc_ip/common_ifs/pins_if.sv
-${PRJ_DIR}/vendor/lowrisc_ip/dv_utils/dv_utils_pkg.sv
-${PRJ_DIR}/vendor/lowrisc_ip/mem_model/mem_model_pkg.sv
+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv
+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.sv
+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv
+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/mem_model/mem_model_pkg.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/irq_agent/irq_if.sv

diff --git a/dv/uvm/icache/doc/ibex_icache_dv_plan.md b/dv/uvm/icache/doc/ibex_icache_dv_plan.md
@@ -20,7 +20,7 @@ The ICache design is documented in the [Instruction Cache](https://ibex-core.rea
 
 ## Testbench architecture
 
-The testbench is built using the [DV_LIB testbench architecture](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/dv_lib/).
+The testbench is built using the [DV_LIB testbench architecture](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/dv/sv/dv_lib/).
 
 The testbench intentionally avoids knowing detailed information about the cache's performance characteristics (for example, cache size, line size or number of ways).
 This means that the testbench cannot compare the DUT with a reference model, nor can it model the exact requests that the DUT will make of instruction memory: the whole point of a cache is that it might avoid an instruction fetch.
@@ -86,7 +86,7 @@ The sole sequence causes occasional 1- or 2-bit errors, injected by XORing valid
 
 The top level testbench is located at [`dv/uvm/icache/dv/tb/tb.sv`](https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/tb/tb.sv). It instantiates the `ibex_icache` DUT module whose source is at [`rtl/ibex_icache.sv`](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_icache.sv).
 In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
-* Clock and reset interface ([`vendor/lowrisc_ip/common_ifs`](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/common_ifs))
+* Clock and reset interface ([`vendor/lowrisc_ip/dv/sv/common_ifs`](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/dv/sv/common_ifs))
 * Core interface ([`dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_if.sv`](https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_if.sv))
 * Memory interface ([`dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_if.sv`](https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_if.sv))
 * ECC interfaces ([`dv/uvm/icache/dv/ibex_icache_ecc_agent/ibex_icache_ecc_if.sv`](https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/ibex_icache_ecc_agent/ibex_icache_ecc_if.sv))
@@ -142,7 +142,7 @@ To do so, we would just need to monitor fetches in the memory agent as well as s
 
 ## Building and running tests
 
-Tests are built and run with the [`dvsim`](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/dvsim) tool (vendored in from the OpenTitan project).
+Tests are built and run with the [`dvsim`](https://github.com/lowRISC/ibex/tree/master/vendor/lowrisc_ip/util/dvsim) tool (vendored in from the OpenTitan project).
 To ensure output files end up in the right place without ugly command lines, this is wrapped up in a Makefile.
 To run the test suite, run:
 

diff --git a/dv/uvm/icache/dv/Makefile b/dv/uvm/icache/dv/Makefile
@@ -30,7 +30,7 @@ TESTS=
 
 ibex-top       := ../../../..
 scratch-root   := $(ibex-top)/build
-dvsim-py       := $(ibex-top)/vendor/lowrisc_ip/dvsim/dvsim.py
+dvsim-py       := $(ibex-top)/vendor/lowrisc_ip/util/dvsim/dvsim.py
 dvsim-std-args := --scratch-root $(scratch-root)
 
 waves-arg      := $(if $(filter-out 0,$(WAVES)),--waves,)

diff --git a/vendor/lowrisc_ip.vendor.hjson b/vendor/lowrisc_ip.vendor.hjson
@@ -11,34 +11,34 @@
     }
 
     mapping: [
-        {from: "hw/dv/sv/common_ifs",  to: "common_ifs"},
-        {from: "hw/dv/sv/csr_utils",   to: "csr_utils"},
-        {from: "hw/dv/sv/dv_base_reg", to: "dv_base_reg"},
-        {from: "hw/dv/sv/mem_model",   to: "mem_model"},
-        {from: "hw/dv/verilator",      to: "dv_verilator"},
+        {from: "hw/dv/sv/common_ifs",  to: "dv/sv/common_ifs"},
+        {from: "hw/dv/sv/csr_utils",   to: "dv/sv/csr_utils"},
+        {from: "hw/dv/sv/dv_base_reg", to: "dv/sv/dv_base_reg"},
+        {from: "hw/dv/sv/mem_model",   to: "dv/sv/mem_model"},
+        {from: "hw/dv/verilator",      to: "dv/verilator"},
 
         // We apply a patch to fix the bus_params_pkg core file name when
         // vendoring in dv_lib and dv_utils. This allows us to have an
         // Ibex-specific core file for these defines.
         {
             from:      "hw/dv/sv/dv_lib",
-            to:        "dv_lib",
+            to:        "dv/sv/dv_lib",
             patch_dir: "dv_lib",
         },
         {
             from:      "hw/dv/sv/dv_utils",
-            to:        "dv_utils",
+            to:        "dv/sv/dv_utils",
             patch_dir: "dv_utils",
         },
 
-        {from: "hw/ip/prim",           to: "prim"},
-        {from: "hw/ip/prim_generic",   to: "prim_generic"},
-        {from: "hw/ip/prim_xilinx",    to: "prim_xilinx"},
+        {from: "hw/ip/prim",           to: "ip/prim"},
+        {from: "hw/ip/prim_generic",   to: "ip/prim_generic"},
+        {from: "hw/ip/prim_xilinx",    to: "ip/prim_xilinx"},
 
         {from: "hw/lint",              to: "lint"},
 
-        {from: "util/dvsim",           to: "dvsim"},
-        {from: "util/uvmdvgen",        to: "uvmdvgen"},
+        {from: "util/dvsim",           to: "util/dvsim"},
+        {from: "util/uvmdvgen",        to: "util/uvmdvgen"},
     ]
 
     patch_dir: "patches/lowrisc_ip"

diff --git a/vendor/lowrisc_ip/common_ifs/clk_if.sv → vendor/lowrisc_ip/dv/sv/common_ifs/clk_if.sv b/vendor/lowrisc_ip/common_ifs/clk_if.sv → vendor/lowrisc_ip/dv/sv/common_ifs/clk_if.sv
diff --git a/vendor/lowrisc_ip/common_ifs/clk_rst_if.sv → ...lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv b/vendor/lowrisc_ip/common_ifs/clk_rst_if.sv → ...lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv
diff --git a/vendor/lowrisc_ip/common_ifs/common_ifs.core → ...wrisc_ip/dv/sv/common_ifs/common_ifs.core b/vendor/lowrisc_ip/common_ifs/common_ifs.core → ...wrisc_ip/dv/sv/common_ifs/common_ifs.core
diff --git a/vendor/lowrisc_ip/common_ifs/index.md → vendor/lowrisc_ip/dv/sv/common_ifs/index.md b/vendor/lowrisc_ip/common_ifs/index.md → vendor/lowrisc_ip/dv/sv/common_ifs/index.md
diff --git a/vendor/lowrisc_ip/common_ifs/pins_if.sv → ...or/lowrisc_ip/dv/sv/common_ifs/pins_if.sv b/vendor/lowrisc_ip/common_ifs/pins_if.sv → ...or/lowrisc_ip/dv/sv/common_ifs/pins_if.sv
diff --git a/vendor/lowrisc_ip/common_ifs/pins_if.svg → ...r/lowrisc_ip/dv/sv/common_ifs/pins_if.svg b/vendor/lowrisc_ip/common_ifs/pins_if.svg → ...r/lowrisc_ip/dv/sv/common_ifs/pins_if.svg
diff --git a/vendor/lowrisc_ip/common_ifs/pins_ifs.core → ...lowrisc_ip/dv/sv/common_ifs/pins_ifs.core b/vendor/lowrisc_ip/common_ifs/pins_ifs.core → ...lowrisc_ip/dv/sv/common_ifs/pins_ifs.core
diff --git a/vendor/lowrisc_ip/csr_utils/README.md → vendor/lowrisc_ip/dv/sv/csr_utils/README.md b/vendor/lowrisc_ip/csr_utils/README.md → vendor/lowrisc_ip/dv/sv/csr_utils/README.md
diff --git a/vendor/lowrisc_ip/csr_utils/csr_seq_lib.sv → ...lowrisc_ip/dv/sv/csr_utils/csr_seq_lib.sv b/vendor/lowrisc_ip/csr_utils/csr_seq_lib.sv → ...lowrisc_ip/dv/sv/csr_utils/csr_seq_lib.sv
diff --git a/vendor/lowrisc_ip/csr_utils/csr_utils.core → ...lowrisc_ip/dv/sv/csr_utils/csr_utils.core b/vendor/lowrisc_ip/csr_utils/csr_utils.core → ...lowrisc_ip/dv/sv/csr_utils/csr_utils.core
diff --git a/vendor/lowrisc_ip/csr_utils/csr_utils_pkg.sv → ...wrisc_ip/dv/sv/csr_utils/csr_utils_pkg.sv b/vendor/lowrisc_ip/csr_utils/csr_utils_pkg.sv → ...wrisc_ip/dv/sv/csr_utils/csr_utils_pkg.sv
diff --git a/...r/lowrisc_ip/dv_base_reg/csr_excl_item.sv → ...isc_ip/dv/sv/dv_base_reg/csr_excl_item.sv b/...r/lowrisc_ip/dv_base_reg/csr_excl_item.sv → ...isc_ip/dv/sv/dv_base_reg/csr_excl_item.sv
diff --git a/vendor/lowrisc_ip/dv_base_reg/dv_base_mem.sv → ...wrisc_ip/dv/sv/dv_base_reg/dv_base_mem.sv b/vendor/lowrisc_ip/dv_base_reg/dv_base_mem.sv → ...wrisc_ip/dv/sv/dv_base_reg/dv_base_mem.sv
diff --git a/...r/lowrisc_ip/dv_base_reg/dv_base_reg.core → ...isc_ip/dv/sv/dv_base_reg/dv_base_reg.core b/...r/lowrisc_ip/dv_base_reg/dv_base_reg.core → ...isc_ip/dv/sv/dv_base_reg/dv_base_reg.core
diff --git a/vendor/lowrisc_ip/dv_base_reg/dv_base_reg.sv → ...wrisc_ip/dv/sv/dv_base_reg/dv_base_reg.sv b/vendor/lowrisc_ip/dv_base_reg/dv_base_reg.sv → ...wrisc_ip/dv/sv/dv_base_reg/dv_base_reg.sv
diff --git a/...wrisc_ip/dv_base_reg/dv_base_reg_block.sv → ...ip/dv/sv/dv_base_reg/dv_base_reg_block.sv b/...wrisc_ip/dv_base_reg/dv_base_reg_block.sv → ...ip/dv/sv/dv_base_reg/dv_base_reg_block.sv
diff --git a/...wrisc_ip/dv_base_reg/dv_base_reg_field.sv → ...ip/dv/sv/dv_base_reg/dv_base_reg_field.sv b/...wrisc_ip/dv_base_reg/dv_base_reg_field.sv → ...ip/dv/sv/dv_base_reg/dv_base_reg_field.sv
diff --git a/...lowrisc_ip/dv_base_reg/dv_base_reg_map.sv → ...c_ip/dv/sv/dv_base_reg/dv_base_reg_map.sv b/...lowrisc_ip/dv_base_reg/dv_base_reg_map.sv → ...c_ip/dv/sv/dv_base_reg/dv_base_reg_map.sv
diff --git a/...lowrisc_ip/dv_base_reg/dv_base_reg_pkg.sv → ...c_ip/dv/sv/dv_base_reg/dv_base_reg_pkg.sv b/...lowrisc_ip/dv_base_reg/dv_base_reg_pkg.sv → ...c_ip/dv/sv/dv_base_reg/dv_base_reg_pkg.sv
diff --git a/vendor/lowrisc_ip/dv_lib/README.md → vendor/lowrisc_ip/dv/sv/dv_lib/README.md b/vendor/lowrisc_ip/dv_lib/README.md → vendor/lowrisc_ip/dv/sv/dv_lib/README.md
diff --git a/vendor/lowrisc_ip/dv_lib/dv_base_agent.sv → .../lowrisc_ip/dv/sv/dv_lib/dv_base_agent.sv b/vendor/lowrisc_ip/dv_lib/dv_base_agent.sv → .../lowrisc_ip/dv/sv/dv_lib/dv_base_agent.sv
diff --git a/...or/lowrisc_ip/dv_lib/dv_base_agent_cfg.sv → ...risc_ip/dv/sv/dv_lib/dv_base_agent_cfg.sv b/...or/lowrisc_ip/dv_lib/dv_base_agent_cfg.sv → ...risc_ip/dv/sv/dv_lib/dv_base_agent_cfg.sv
diff --git a/...or/lowrisc_ip/dv_lib/dv_base_agent_cov.sv → ...risc_ip/dv/sv/dv_lib/dv_base_agent_cov.sv b/...or/lowrisc_ip/dv_lib/dv_base_agent_cov.sv → ...risc_ip/dv/sv/dv_lib/dv_base_agent_cov.sv
diff --git a/vendor/lowrisc_ip/dv_lib/dv_base_driver.sv → ...lowrisc_ip/dv/sv/dv_lib/dv_base_driver.sv b/vendor/lowrisc_ip/dv_lib/dv_base_driver.sv → ...lowrisc_ip/dv/sv/dv_lib/dv_base_driver.sv
diff --git a/vendor/lowrisc_ip/dv_lib/dv_base_env.sv → ...or/lowrisc_ip/dv/sv/dv_lib/dv_base_env.sv b/vendor/lowrisc_ip/dv_lib/dv_base_env.sv → ...or/lowrisc_ip/dv/sv/dv_lib/dv_base_env.sv
diff --git a/vendor/lowrisc_ip/dv_lib/dv_base_env_cfg.sv → ...owrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv b/vendor/lowrisc_ip/dv_lib/dv_base_env_cfg.sv → ...owrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv
diff --git a/vendor/lowrisc_ip/dv_lib/dv_base_env_cov.sv → ...owrisc_ip/dv/sv/dv_lib/dv_base_env_cov.sv b/vendor/lowrisc_ip/dv_lib/dv_base_env_cov.sv → ...owrisc_ip/dv/sv/dv_lib/dv_base_env_cov.sv
diff --git a/vendor/lowrisc_ip/dv_lib/dv_base_monitor.sv → ...owrisc_ip/dv/sv/dv_lib/dv_base_monitor.sv b/vendor/lowrisc_ip/dv_lib/dv_base_monitor.sv → ...owrisc_ip/dv/sv/dv_lib/dv_base_monitor.sv
diff --git a/...r/lowrisc_ip/dv_lib/dv_base_scoreboard.sv → ...isc_ip/dv/sv/dv_lib/dv_base_scoreboard.sv b/...r/lowrisc_ip/dv_lib/dv_base_scoreboard.sv → ...isc_ip/dv/sv/dv_lib/dv_base_scoreboard.sv
diff --git a/vendor/lowrisc_ip/dv_lib/dv_base_seq.sv → ...or/lowrisc_ip/dv/sv/dv_lib/dv_base_seq.sv b/vendor/lowrisc_ip/dv_lib/dv_base_seq.sv → ...or/lowrisc_ip/dv/sv/dv_lib/dv_base_seq.sv
diff --git a/...or/lowrisc_ip/dv_lib/dv_base_sequencer.sv → ...risc_ip/dv/sv/dv_lib/dv_base_sequencer.sv b/...or/lowrisc_ip/dv_lib/dv_base_sequencer.sv → ...risc_ip/dv/sv/dv_lib/dv_base_sequencer.sv
diff --git a/vendor/lowrisc_ip/dv_lib/dv_base_test.sv → ...r/lowrisc_ip/dv/sv/dv_lib/dv_base_test.sv b/vendor/lowrisc_ip/dv_lib/dv_base_test.sv → ...r/lowrisc_ip/dv/sv/dv_lib/dv_base_test.sv
diff --git a/...sc_ip/dv_lib/dv_base_virtual_sequencer.sv → ...dv/sv/dv_lib/dv_base_virtual_sequencer.sv b/...sc_ip/dv_lib/dv_base_virtual_sequencer.sv → ...dv/sv/dv_lib/dv_base_virtual_sequencer.sv
diff --git a/vendor/lowrisc_ip/dv_lib/dv_base_vseq.sv → ...r/lowrisc_ip/dv/sv/dv_lib/dv_base_vseq.sv b/vendor/lowrisc_ip/dv_lib/dv_base_vseq.sv → ...r/lowrisc_ip/dv/sv/dv_lib/dv_base_vseq.sv
diff --git a/vendor/lowrisc_ip/dv_lib/dv_lib.core → vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib.core b/vendor/lowrisc_ip/dv_lib/dv_lib.core → vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib.core
diff --git a/vendor/lowrisc_ip/dv_lib/dv_lib_pkg.sv → vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib_pkg.sv b/vendor/lowrisc_ip/dv_lib/dv_lib_pkg.sv → vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib_pkg.sv
diff --git a/vendor/lowrisc_ip/dv_utils/README.md → vendor/lowrisc_ip/dv/sv/dv_utils/README.md b/vendor/lowrisc_ip/dv_utils/README.md → vendor/lowrisc_ip/dv/sv/dv_utils/README.md
diff --git a/vendor/lowrisc_ip/dv_utils/dv_macros.svh → ...r/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh b/vendor/lowrisc_ip/dv_utils/dv_macros.svh → ...r/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh
diff --git a/...r/lowrisc_ip/dv_utils/dv_report_server.sv → ...isc_ip/dv/sv/dv_utils/dv_report_server.sv b/...r/lowrisc_ip/dv_utils/dv_report_server.sv → ...isc_ip/dv/sv/dv_utils/dv_report_server.sv
diff --git a/vendor/lowrisc_ip/dv_utils/dv_utils.core → ...r/lowrisc_ip/dv/sv/dv_utils/dv_utils.core b/vendor/lowrisc_ip/dv_utils/dv_utils.core → ...r/lowrisc_ip/dv/sv/dv_utils/dv_utils.core
diff --git a/vendor/lowrisc_ip/dv_utils/dv_utils_pkg.sv → ...lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv b/vendor/lowrisc_ip/dv_utils/dv_utils_pkg.sv → ...lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv
diff --git a/vendor/lowrisc_ip/mem_model/README.md → vendor/lowrisc_ip/dv/sv/mem_model/README.md b/vendor/lowrisc_ip/mem_model/README.md → vendor/lowrisc_ip/dv/sv/mem_model/README.md
diff --git a/vendor/lowrisc_ip/mem_model/mem_model.core → ...lowrisc_ip/dv/sv/mem_model/mem_model.core b/vendor/lowrisc_ip/mem_model/mem_model.core → ...lowrisc_ip/dv/sv/mem_model/mem_model.core
diff --git a/vendor/lowrisc_ip/mem_model/mem_model.sv → ...r/lowrisc_ip/dv/sv/mem_model/mem_model.sv b/vendor/lowrisc_ip/mem_model/mem_model.sv → ...r/lowrisc_ip/dv/sv/mem_model/mem_model.sv
diff --git a/vendor/lowrisc_ip/mem_model/mem_model_pkg.sv → ...wrisc_ip/dv/sv/mem_model/mem_model_pkg.sv b/vendor/lowrisc_ip/mem_model/mem_model_pkg.sv → ...wrisc_ip/dv/sv/mem_model/mem_model_pkg.sv
diff --git a/vendor/lowrisc_ip/dv_verilator/README.md → vendor/lowrisc_ip/dv/verilator/README.md b/vendor/lowrisc_ip/dv_verilator/README.md → vendor/lowrisc_ip/dv/verilator/README.md
diff --git a/..._ip/dv_verilator/cpp/verilator_memutil.cc → ..._ip/dv/verilator/cpp/verilator_memutil.cc b/..._ip/dv_verilator/cpp/verilator_memutil.cc → ..._ip/dv/verilator/cpp/verilator_memutil.cc
diff --git a/...c_ip/dv_verilator/cpp/verilator_memutil.h → ...c_ip/dv/verilator/cpp/verilator_memutil.h b/...c_ip/dv_verilator/cpp/verilator_memutil.h → ...c_ip/dv/verilator/cpp/verilator_memutil.h
diff --git a/...sc_ip/dv_verilator/memutil_verilator.core → ...sc_ip/dv/verilator/memutil_verilator.core b/...sc_ip/dv_verilator/memutil_verilator.core → ...sc_ip/dv/verilator/memutil_verilator.core
diff --git a/...imutil_verilator/cpp/sim_ctrl_extension.h → ...imutil_verilator/cpp/sim_ctrl_extension.h b/...imutil_verilator/cpp/sim_ctrl_extension.h → ...imutil_verilator/cpp/sim_ctrl_extension.h
diff --git a/...mutil_verilator/cpp/verilated_toplevel.cc → ...mutil_verilator/cpp/verilated_toplevel.cc b/...mutil_verilator/cpp/verilated_toplevel.cc → ...mutil_verilator/cpp/verilated_toplevel.cc
diff --git a/...imutil_verilator/cpp/verilated_toplevel.h → ...imutil_verilator/cpp/verilated_toplevel.h b/...imutil_verilator/cpp/verilated_toplevel.h → ...imutil_verilator/cpp/verilated_toplevel.h
diff --git a/...mutil_verilator/cpp/verilator_sim_ctrl.cc → ...mutil_verilator/cpp/verilator_sim_ctrl.cc b/...mutil_verilator/cpp/verilator_sim_ctrl.cc → ...mutil_verilator/cpp/verilator_sim_ctrl.cc
diff --git a/...imutil_verilator/cpp/verilator_sim_ctrl.h → ...imutil_verilator/cpp/verilator_sim_ctrl.h b/...imutil_verilator/cpp/verilator_sim_ctrl.h → ...imutil_verilator/cpp/verilator_sim_ctrl.h
diff --git a/.../simutil_verilator/simutil_verilator.core → .../simutil_verilator/simutil_verilator.core b/.../simutil_verilator/simutil_verilator.core → .../simutil_verilator/simutil_verilator.core
diff --git a/vendor/lowrisc_ip/prim/README.md → vendor/lowrisc_ip/ip/prim/README.md b/vendor/lowrisc_ip/prim/README.md → vendor/lowrisc_ip/ip/prim/README.md
diff --git a/vendor/lowrisc_ip/prim/doc/prim_keccak.md → vendor/lowrisc_ip/ip/prim/doc/prim_keccak.md b/vendor/lowrisc_ip/prim/doc/prim_keccak.md → vendor/lowrisc_ip/ip/prim/doc/prim_keccak.md
diff --git a/vendor/lowrisc_ip/prim/doc/prim_lfsr.md → vendor/lowrisc_ip/ip/prim/doc/prim_lfsr.md b/vendor/lowrisc_ip/prim/doc/prim_lfsr.md → vendor/lowrisc_ip/ip/prim/doc/prim_lfsr.md
diff --git a/vendor/lowrisc_ip/prim/doc/prim_packer.md → vendor/lowrisc_ip/ip/prim/doc/prim_packer.md b/vendor/lowrisc_ip/prim/doc/prim_packer.md → vendor/lowrisc_ip/ip/prim/doc/prim_packer.md
diff --git a/vendor/lowrisc_ip/prim/doc/prim_present.md → ...or/lowrisc_ip/ip/prim/doc/prim_present.md b/vendor/lowrisc_ip/prim/doc/prim_present.md → ...or/lowrisc_ip/ip/prim/doc/prim_present.md
diff --git a/vendor/lowrisc_ip/prim/doc/prim_prince.md → vendor/lowrisc_ip/ip/prim/doc/prim_prince.md b/vendor/lowrisc_ip/prim/doc/prim_prince.md → vendor/lowrisc_ip/ip/prim/doc/prim_prince.md
diff --git a/...c_ip/prim/dv/prim_lfsr/prim_lfsr_sim.core → ...p/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core b/...c_ip/prim/dv/prim_lfsr/prim_lfsr_sim.core → ...p/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core
diff --git a/...prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson → ...prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson b/...prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson → ...prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson
diff --git a/...rim/dv/prim_lfsr/prim_lfsr_testplan.hjson → ...rim/dv/prim_lfsr/prim_lfsr_testplan.hjson b/...rim/dv/prim_lfsr/prim_lfsr_testplan.hjson → ...rim/dv/prim_lfsr/prim_lfsr_testplan.hjson
diff --git a/...c_ip/prim/dv/prim_lfsr/tb/prim_lfsr_tb.sv → ...p/ip/prim/dv/prim_lfsr/tb/prim_lfsr_tb.sv b/...c_ip/prim/dv/prim_lfsr/tb/prim_lfsr_tb.sv → ...p/ip/prim/dv/prim_lfsr/tb/prim_lfsr_tb.sv
diff --git a/...prim_present/crypto_dpi_present/boxes.inc → ...prim_present/crypto_dpi_present/boxes.inc b/...prim_present/crypto_dpi_present/boxes.inc → ...prim_present/crypto_dpi_present/boxes.inc
diff --git a/...im_present/crypto_dpi_present/comline.inc → ...im_present/crypto_dpi_present/comline.inc b/...im_present/crypto_dpi_present/comline.inc → ...im_present/crypto_dpi_present/comline.inc
diff --git a/...t/crypto_dpi_present/crypto_dpi_present.c → ...t/crypto_dpi_present/crypto_dpi_present.c b/...t/crypto_dpi_present/crypto_dpi_present.c → ...t/crypto_dpi_present/crypto_dpi_present.c
diff --git a/...rypto_dpi_present/crypto_dpi_present.core → ...rypto_dpi_present/crypto_dpi_present.core b/...rypto_dpi_present/crypto_dpi_present.core → ...rypto_dpi_present/crypto_dpi_present.core
diff --git a/...pto_dpi_present/crypto_dpi_present_pkg.sv → ...pto_dpi_present/crypto_dpi_present_pkg.sv b/...pto_dpi_present/crypto_dpi_present_pkg.sv → ...pto_dpi_present/crypto_dpi_present_pkg.sv
diff --git a/...im_present/crypto_dpi_present/present.inc → ...im_present/crypto_dpi_present/present.inc b/...im_present/crypto_dpi_present/present.inc → ...im_present/crypto_dpi_present/present.inc
diff --git a/...im_present/crypto_dpi_present/verbose.inc → ...im_present/crypto_dpi_present/verbose.inc b/...im_present/crypto_dpi_present/verbose.inc → ...im_present/crypto_dpi_present/verbose.inc
diff --git a/.../prim_present/data/prim_present_cover.cfg → .../prim_present/data/prim_present_cover.cfg b/.../prim_present/data/prim_present_cover.cfg → .../prim_present/data/prim_present_cover.cfg
diff --git a/..._present/data/prim_present_testplan.hjson → ..._present/data/prim_present_testplan.hjson b/..._present/data/prim_present_testplan.hjson → ..._present/data/prim_present_testplan.hjson
diff --git a/...rim/dv/prim_present/prim_present_sim.core → ...rim/dv/prim_present/prim_present_sim.core b/...rim/dv/prim_present/prim_present_sim.core → ...rim/dv/prim_present/prim_present_sim.core
diff --git a/...v/prim_present/prim_present_sim_cfg.hjson → ...v/prim_present/prim_present_sim_cfg.hjson b/...v/prim_present/prim_present_sim_cfg.hjson → ...v/prim_present/prim_present_sim_cfg.hjson
diff --git a/...rim/dv/prim_present/tb/prim_present_tb.sv → ...rim/dv/prim_present/tb/prim_present_tb.sv b/...rim/dv/prim_present/tb/prim_present_tb.sv → ...rim/dv/prim_present/tb/prim_present_tb.sv
diff --git a/...p/prim/fpv/prim_alert_rxtx_async_fpv.core → ...p/prim/fpv/prim_alert_rxtx_async_fpv.core b/...p/prim/fpv/prim_alert_rxtx_async_fpv.core → ...p/prim/fpv/prim_alert_rxtx_async_fpv.core
diff --git a/...risc_ip/prim/fpv/prim_alert_rxtx_fpv.core → ...c_ip/ip/prim/fpv/prim_alert_rxtx_fpv.core b/...risc_ip/prim/fpv/prim_alert_rxtx_fpv.core → ...c_ip/ip/prim/fpv/prim_alert_rxtx_fpv.core
diff --git a/...c_ip/prim/fpv/prim_arbiter_fixed_fpv.core → ...p/ip/prim/fpv/prim_arbiter_fixed_fpv.core b/...c_ip/prim/fpv/prim_arbiter_fixed_fpv.core → ...p/ip/prim/fpv/prim_arbiter_fixed_fpv.core
diff --git a/...isc_ip/prim/fpv/prim_arbiter_ppc_fpv.core → ..._ip/ip/prim/fpv/prim_arbiter_ppc_fpv.core b/...isc_ip/prim/fpv/prim_arbiter_ppc_fpv.core → ..._ip/ip/prim/fpv/prim_arbiter_ppc_fpv.core
diff --git a/...sc_ip/prim/fpv/prim_arbiter_tree_fpv.core → ...ip/ip/prim/fpv/prim_arbiter_tree_fpv.core b/...sc_ip/prim/fpv/prim_arbiter_tree_fpv.core → ...ip/ip/prim/fpv/prim_arbiter_tree_fpv.core
diff --git a/...owrisc_ip/prim/fpv/prim_esc_rxtx_fpv.core → ...isc_ip/ip/prim/fpv/prim_esc_rxtx_fpv.core b/...owrisc_ip/prim/fpv/prim_esc_rxtx_fpv.core → ...isc_ip/ip/prim/fpv/prim_esc_rxtx_fpv.core
diff --git a/...wrisc_ip/prim/fpv/prim_fifo_sync_fpv.core → ...sc_ip/ip/prim/fpv/prim_fifo_sync_fpv.core b/...wrisc_ip/prim/fpv/prim_fifo_sync_fpv.core → ...sc_ip/ip/prim/fpv/prim_fifo_sync_fpv.core
diff --git a/.../lowrisc_ip/prim/fpv/prim_keccak_fpv.core → ...wrisc_ip/ip/prim/fpv/prim_keccak_fpv.core b/.../lowrisc_ip/prim/fpv/prim_keccak_fpv.core → ...wrisc_ip/ip/prim/fpv/prim_keccak_fpv.core
diff --git a/...or/lowrisc_ip/prim/fpv/prim_lfsr_fpv.core → ...lowrisc_ip/ip/prim/fpv/prim_lfsr_fpv.core b/...or/lowrisc_ip/prim/fpv/prim_lfsr_fpv.core → ...lowrisc_ip/ip/prim/fpv/prim_lfsr_fpv.core
diff --git a/.../fpv/tb/prim_alert_rxtx_async_bind_fpv.sv → .../fpv/tb/prim_alert_rxtx_async_bind_fpv.sv b/.../fpv/tb/prim_alert_rxtx_async_bind_fpv.sv → .../fpv/tb/prim_alert_rxtx_async_bind_fpv.sv
diff --git a/.../prim/fpv/tb/prim_alert_rxtx_async_fpv.sv → .../prim/fpv/tb/prim_alert_rxtx_async_fpv.sv b/.../prim/fpv/tb/prim_alert_rxtx_async_fpv.sv → .../prim/fpv/tb/prim_alert_rxtx_async_fpv.sv
diff --git a/...p/prim/fpv/tb/prim_alert_rxtx_bind_fpv.sv → ...p/prim/fpv/tb/prim_alert_rxtx_bind_fpv.sv b/...p/prim/fpv/tb/prim_alert_rxtx_bind_fpv.sv → ...p/prim/fpv/tb/prim_alert_rxtx_bind_fpv.sv
diff --git a/...isc_ip/prim/fpv/tb/prim_alert_rxtx_fpv.sv → ..._ip/ip/prim/fpv/tb/prim_alert_rxtx_fpv.sv b/...isc_ip/prim/fpv/tb/prim_alert_rxtx_fpv.sv → ..._ip/ip/prim/fpv/tb/prim_alert_rxtx_fpv.sv
diff --git a/..._ip/prim/fpv/tb/prim_arbiter_fixed_fpv.sv → .../ip/prim/fpv/tb/prim_arbiter_fixed_fpv.sv b/..._ip/prim/fpv/tb/prim_arbiter_fixed_fpv.sv → .../ip/prim/fpv/tb/prim_arbiter_fixed_fpv.sv
diff --git a/...sc_ip/prim/fpv/tb/prim_arbiter_ppc_fpv.sv → ...ip/ip/prim/fpv/tb/prim_arbiter_ppc_fpv.sv b/...sc_ip/prim/fpv/tb/prim_arbiter_ppc_fpv.sv → ...ip/ip/prim/fpv/tb/prim_arbiter_ppc_fpv.sv
diff --git a/...c_ip/prim/fpv/tb/prim_arbiter_tree_fpv.sv → ...p/ip/prim/fpv/tb/prim_arbiter_tree_fpv.sv b/...c_ip/prim/fpv/tb/prim_arbiter_tree_fpv.sv → ...p/ip/prim/fpv/tb/prim_arbiter_tree_fpv.sv
diff --git a/..._ip/prim/fpv/tb/prim_esc_rxtx_bind_fpv.sv → .../ip/prim/fpv/tb/prim_esc_rxtx_bind_fpv.sv b/..._ip/prim/fpv/tb/prim_esc_rxtx_bind_fpv.sv → .../ip/prim/fpv/tb/prim_esc_rxtx_bind_fpv.sv
diff --git a/...wrisc_ip/prim/fpv/tb/prim_esc_rxtx_fpv.sv → ...sc_ip/ip/prim/fpv/tb/prim_esc_rxtx_fpv.sv b/...wrisc_ip/prim/fpv/tb/prim_esc_rxtx_fpv.sv → ...sc_ip/ip/prim/fpv/tb/prim_esc_rxtx_fpv.sv
diff --git a/...ip/prim/fpv/tb/prim_fifo_sync_bind_fpv.sv → ...ip/prim/fpv/tb/prim_fifo_sync_bind_fpv.sv b/...ip/prim/fpv/tb/prim_fifo_sync_bind_fpv.sv → ...ip/prim/fpv/tb/prim_fifo_sync_bind_fpv.sv
diff --git a/...risc_ip/prim/fpv/tb/prim_fifo_sync_fpv.sv → ...c_ip/ip/prim/fpv/tb/prim_fifo_sync_fpv.sv b/...risc_ip/prim/fpv/tb/prim_fifo_sync_fpv.sv → ...c_ip/ip/prim/fpv/tb/prim_fifo_sync_fpv.sv
diff --git a/...lowrisc_ip/prim/fpv/tb/prim_keccak_fpv.sv → ...risc_ip/ip/prim/fpv/tb/prim_keccak_fpv.sv b/...lowrisc_ip/prim/fpv/tb/prim_keccak_fpv.sv → ...risc_ip/ip/prim/fpv/tb/prim_keccak_fpv.sv
diff --git a/...r/lowrisc_ip/prim/fpv/tb/prim_lfsr_fpv.sv → ...owrisc_ip/ip/prim/fpv/tb/prim_lfsr_fpv.sv b/...r/lowrisc_ip/prim/fpv/tb/prim_lfsr_fpv.sv → ...owrisc_ip/ip/prim/fpv/tb/prim_lfsr_fpv.sv
diff --git a/...rim/fpv/vip/prim_alert_rxtx_assert_fpv.sv → ...rim/fpv/vip/prim_alert_rxtx_assert_fpv.sv b/...rim/fpv/vip/prim_alert_rxtx_assert_fpv.sv → ...rim/fpv/vip/prim_alert_rxtx_assert_fpv.sv
diff --git a/...v/vip/prim_alert_rxtx_async_assert_fpv.sv → ...v/vip/prim_alert_rxtx_async_assert_fpv.sv b/...v/vip/prim_alert_rxtx_async_assert_fpv.sv → ...v/vip/prim_alert_rxtx_async_assert_fpv.sv
diff --git a/.../prim/fpv/vip/prim_esc_rxtx_assert_fpv.sv → .../prim/fpv/vip/prim_esc_rxtx_assert_fpv.sv b/.../prim/fpv/vip/prim_esc_rxtx_assert_fpv.sv → .../prim/fpv/vip/prim_esc_rxtx_assert_fpv.sv
diff --git a/...prim/fpv/vip/prim_fifo_sync_assert_fpv.sv → ...prim/fpv/vip/prim_fifo_sync_assert_fpv.sv b/...prim/fpv/vip/prim_fifo_sync_assert_fpv.sv → ...prim/fpv/vip/prim_fifo_sync_assert_fpv.sv
diff --git a/vendor/lowrisc_ip/prim/lint/prim.vlt → vendor/lowrisc_ip/ip/prim/lint/prim.vlt b/vendor/lowrisc_ip/prim/lint/prim.vlt → vendor/lowrisc_ip/ip/prim/lint/prim.vlt
diff --git a/vendor/lowrisc_ip/prim/lint/prim.waiver → vendor/lowrisc_ip/ip/prim/lint/prim.waiver b/vendor/lowrisc_ip/prim/lint/prim.waiver → vendor/lowrisc_ip/ip/prim/lint/prim.waiver
diff --git a/...ip/prim/pre_dv/prim_sync_reqack/README.md → ...ip/prim/pre_dv/prim_sync_reqack/README.md b/...ip/prim/pre_dv/prim_sync_reqack/README.md → ...ip/prim/pre_dv/prim_sync_reqack/README.md
diff --git a/...im_sync_reqack/cpp/prim_sync_reqack_tb.cc → ...im_sync_reqack/cpp/prim_sync_reqack_tb.cc b/...im_sync_reqack/cpp/prim_sync_reqack_tb.cc → ...im_sync_reqack/cpp/prim_sync_reqack_tb.cc
diff --git a/...prim_sync_reqack/prim_sync_reqack_tb.core → ...prim_sync_reqack/prim_sync_reqack_tb.core b/...prim_sync_reqack/prim_sync_reqack_tb.core → ...prim_sync_reqack/prim_sync_reqack_tb.core
diff --git a/...im_sync_reqack/rtl/prim_sync_reqack_tb.sv → ...im_sync_reqack/rtl/prim_sync_reqack_tb.sv b/...im_sync_reqack/rtl/prim_sync_reqack_tb.sv → ...im_sync_reqack/rtl/prim_sync_reqack_tb.sv
diff --git a/vendor/lowrisc_ip/prim/prim.core → vendor/lowrisc_ip/ip/prim/prim.core b/vendor/lowrisc_ip/prim/prim.core → vendor/lowrisc_ip/ip/prim/prim.core
diff --git a/vendor/lowrisc_ip/prim/prim_assert.core → vendor/lowrisc_ip/ip/prim/prim_assert.core b/vendor/lowrisc_ip/prim/prim_assert.core → vendor/lowrisc_ip/ip/prim/prim_assert.core
diff --git a/vendor/lowrisc_ip/prim/prim_clock_buf.core → ...or/lowrisc_ip/ip/prim/prim_clock_buf.core b/vendor/lowrisc_ip/prim/prim_clock_buf.core → ...or/lowrisc_ip/ip/prim/prim_clock_buf.core
diff --git a/...or/lowrisc_ip/prim/prim_clock_gating.core → ...lowrisc_ip/ip/prim/prim_clock_gating.core b/...or/lowrisc_ip/prim/prim_clock_gating.core → ...lowrisc_ip/ip/prim/prim_clock_gating.core
diff --git a/vendor/lowrisc_ip/prim/prim_clock_inv.core → ...or/lowrisc_ip/ip/prim/prim_clock_inv.core b/vendor/lowrisc_ip/prim/prim_clock_inv.core → ...or/lowrisc_ip/ip/prim/prim_clock_inv.core
diff --git a/vendor/lowrisc_ip/prim/prim_clock_mux2.core → ...r/lowrisc_ip/ip/prim/prim_clock_mux2.core b/vendor/lowrisc_ip/prim/prim_clock_mux2.core → ...r/lowrisc_ip/ip/prim/prim_clock_mux2.core
diff --git a/vendor/lowrisc_ip/prim/prim_diff_decode.core → .../lowrisc_ip/ip/prim/prim_diff_decode.core b/vendor/lowrisc_ip/prim/prim_diff_decode.core → .../lowrisc_ip/ip/prim/prim_diff_decode.core
diff --git a/.../lowrisc_ip/prim/prim_dom_and_2share.core → ...wrisc_ip/ip/prim/prim_dom_and_2share.core b/.../lowrisc_ip/prim/prim_dom_and_2share.core → ...wrisc_ip/ip/prim/prim_dom_and_2share.core
diff --git a/vendor/lowrisc_ip/prim/prim_flash.core → vendor/lowrisc_ip/ip/prim/prim_flash.core b/vendor/lowrisc_ip/prim/prim_flash.core → vendor/lowrisc_ip/ip/prim/prim_flash.core
diff --git a/vendor/lowrisc_ip/prim/prim_flop.core → vendor/lowrisc_ip/ip/prim/prim_flop.core b/vendor/lowrisc_ip/prim/prim_flop.core → vendor/lowrisc_ip/ip/prim/prim_flop.core
diff --git a/vendor/lowrisc_ip/prim/prim_flop_2sync.core → ...r/lowrisc_ip/ip/prim/prim_flop_2sync.core b/vendor/lowrisc_ip/prim/prim_flop_2sync.core → ...r/lowrisc_ip/ip/prim/prim_flop_2sync.core
diff --git a/vendor/lowrisc_ip/prim/prim_gf_mult.core → vendor/lowrisc_ip/ip/prim/prim_gf_mult.core b/vendor/lowrisc_ip/prim/prim_gf_mult.core → vendor/lowrisc_ip/ip/prim/prim_gf_mult.core
diff --git a/vendor/lowrisc_ip/prim/prim_lfsr.core → vendor/lowrisc_ip/ip/prim/prim_lfsr.core b/vendor/lowrisc_ip/prim/prim_lfsr.core → vendor/lowrisc_ip/ip/prim/prim_lfsr.core
diff --git a/vendor/lowrisc_ip/prim/prim_otp.core → vendor/lowrisc_ip/ip/prim/prim_otp.core b/vendor/lowrisc_ip/prim/prim_otp.core → vendor/lowrisc_ip/ip/prim/prim_otp.core
diff --git a/vendor/lowrisc_ip/prim/prim_pad_wrapper.core → .../lowrisc_ip/ip/prim/prim_pad_wrapper.core b/vendor/lowrisc_ip/prim/prim_pad_wrapper.core → .../lowrisc_ip/ip/prim/prim_pad_wrapper.core
diff --git a/vendor/lowrisc_ip/prim/prim_pkg.core → vendor/lowrisc_ip/ip/prim/prim_pkg.core b/vendor/lowrisc_ip/prim/prim_pkg.core → vendor/lowrisc_ip/ip/prim/prim_pkg.core
diff --git a/vendor/lowrisc_ip/prim/prim_ram_1p.core → vendor/lowrisc_ip/ip/prim/prim_ram_1p.core b/vendor/lowrisc_ip/prim/prim_ram_1p.core → vendor/lowrisc_ip/ip/prim/prim_ram_1p.core
diff --git a/vendor/lowrisc_ip/prim/prim_ram_1p_adv.core → ...r/lowrisc_ip/ip/prim/prim_ram_1p_adv.core b/vendor/lowrisc_ip/prim/prim_ram_1p_adv.core → ...r/lowrisc_ip/ip/prim/prim_ram_1p_adv.core
diff --git a/vendor/lowrisc_ip/prim/prim_ram_1p_scr.core → ...r/lowrisc_ip/ip/prim/prim_ram_1p_scr.core b/vendor/lowrisc_ip/prim/prim_ram_1p_scr.core → ...r/lowrisc_ip/ip/prim/prim_ram_1p_scr.core
diff --git a/vendor/lowrisc_ip/prim/prim_ram_2p.core → vendor/lowrisc_ip/ip/prim/prim_ram_2p.core b/vendor/lowrisc_ip/prim/prim_ram_2p.core → vendor/lowrisc_ip/ip/prim/prim_ram_2p.core
diff --git a/vendor/lowrisc_ip/prim/prim_ram_2p_adv.core → ...r/lowrisc_ip/ip/prim/prim_ram_2p_adv.core b/vendor/lowrisc_ip/prim/prim_ram_2p_adv.core → ...r/lowrisc_ip/ip/prim/prim_ram_2p_adv.core
diff --git a/...owrisc_ip/prim/prim_ram_2p_async_adv.core → ...isc_ip/ip/prim/prim_ram_2p_async_adv.core b/...owrisc_ip/prim/prim_ram_2p_async_adv.core → ...isc_ip/ip/prim/prim_ram_2p_async_adv.core
diff --git a/vendor/lowrisc_ip/prim/prim_rom.core → vendor/lowrisc_ip/ip/prim/prim_rom.core b/vendor/lowrisc_ip/prim/prim_rom.core → vendor/lowrisc_ip/ip/prim/prim_rom.core
diff --git a/vendor/lowrisc_ip/prim/prim_rom_adv.core → vendor/lowrisc_ip/ip/prim/prim_rom_adv.core b/vendor/lowrisc_ip/prim/prim_rom_adv.core → vendor/lowrisc_ip/ip/prim/prim_rom_adv.core
diff --git a/vendor/lowrisc_ip/prim/prim_secded.core → vendor/lowrisc_ip/ip/prim/prim_secded.core b/vendor/lowrisc_ip/prim/prim_secded.core → vendor/lowrisc_ip/ip/prim/prim_secded.core
diff --git a/vendor/lowrisc_ip/prim/prim_util.core → vendor/lowrisc_ip/ip/prim/prim_util.core b/vendor/lowrisc_ip/prim/prim_util.core → vendor/lowrisc_ip/ip/prim/prim_util.core
diff --git a/...or/lowrisc_ip/prim/prim_util_memload.core → ...lowrisc_ip/ip/prim/prim_util_memload.core b/...or/lowrisc_ip/prim/prim_util_memload.core → ...lowrisc_ip/ip/prim/prim_util_memload.core
diff --git a/vendor/lowrisc_ip/prim/primgen.core → vendor/lowrisc_ip/ip/prim/primgen.core b/vendor/lowrisc_ip/prim/primgen.core → vendor/lowrisc_ip/ip/prim/primgen.core
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_alert_pkg.sv → .../lowrisc_ip/ip/prim/rtl/prim_alert_pkg.sv b/vendor/lowrisc_ip/prim/rtl/prim_alert_pkg.sv → .../lowrisc_ip/ip/prim/rtl/prim_alert_pkg.sv
diff --git a/...owrisc_ip/prim/rtl/prim_alert_receiver.sv → ...isc_ip/ip/prim/rtl/prim_alert_receiver.sv b/...owrisc_ip/prim/rtl/prim_alert_receiver.sv → ...isc_ip/ip/prim/rtl/prim_alert_receiver.sv
diff --git a/.../lowrisc_ip/prim/rtl/prim_alert_sender.sv → ...wrisc_ip/ip/prim/rtl/prim_alert_sender.sv b/.../lowrisc_ip/prim/rtl/prim_alert_sender.sv → ...wrisc_ip/ip/prim/rtl/prim_alert_sender.sv
diff --git a/...lowrisc_ip/prim/rtl/prim_arbiter_fixed.sv → ...risc_ip/ip/prim/rtl/prim_arbiter_fixed.sv b/...lowrisc_ip/prim/rtl/prim_arbiter_fixed.sv → ...risc_ip/ip/prim/rtl/prim_arbiter_fixed.sv
diff --git a/...r/lowrisc_ip/prim/rtl/prim_arbiter_ppc.sv → ...owrisc_ip/ip/prim/rtl/prim_arbiter_ppc.sv b/...r/lowrisc_ip/prim/rtl/prim_arbiter_ppc.sv → ...owrisc_ip/ip/prim/rtl/prim_arbiter_ppc.sv
diff --git a/.../lowrisc_ip/prim/rtl/prim_arbiter_tree.sv → ...wrisc_ip/ip/prim/rtl/prim_arbiter_tree.sv b/.../lowrisc_ip/prim/rtl/prim_arbiter_tree.sv → ...wrisc_ip/ip/prim/rtl/prim_arbiter_tree.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_assert.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv b/vendor/lowrisc_ip/prim/rtl/prim_assert.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv
diff --git a/..._ip/prim/rtl/prim_assert_dummy_macros.svh → .../ip/prim/rtl/prim_assert_dummy_macros.svh b/..._ip/prim/rtl/prim_assert_dummy_macros.svh → .../ip/prim/rtl/prim_assert_dummy_macros.svh
diff --git a/.../prim/rtl/prim_assert_standard_macros.svh → .../prim/rtl/prim_assert_standard_macros.svh b/.../prim/rtl/prim_assert_standard_macros.svh → .../prim/rtl/prim_assert_standard_macros.svh
diff --git a/..._ip/prim/rtl/prim_assert_yosys_macros.svh → .../ip/prim/rtl/prim_assert_yosys_macros.svh b/..._ip/prim/rtl/prim_assert_yosys_macros.svh → .../ip/prim/rtl/prim_assert_yosys_macros.svh
diff --git a/...or/lowrisc_ip/prim/rtl/prim_cipher_pkg.sv → ...lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv b/...or/lowrisc_ip/prim/rtl/prim_cipher_pkg.sv → ...lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv
diff --git a/...isc_ip/prim/rtl/prim_clock_gating_sync.sv → ..._ip/ip/prim/rtl/prim_clock_gating_sync.sv b/...isc_ip/prim/rtl/prim_clock_gating_sync.sv → ..._ip/ip/prim/rtl/prim_clock_gating_sync.sv
diff --git a/...r/lowrisc_ip/prim/rtl/prim_diff_decode.sv → ...owrisc_ip/ip/prim/rtl/prim_diff_decode.sv b/...r/lowrisc_ip/prim/rtl/prim_diff_decode.sv → ...owrisc_ip/ip/prim/rtl/prim_diff_decode.sv
diff --git a/...owrisc_ip/prim/rtl/prim_dom_and_2share.sv → ...isc_ip/ip/prim/rtl/prim_dom_and_2share.sv b/...owrisc_ip/prim/rtl/prim_dom_and_2share.sv → ...isc_ip/ip/prim/rtl/prim_dom_and_2share.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_esc_pkg.sv → ...or/lowrisc_ip/ip/prim/rtl/prim_esc_pkg.sv b/vendor/lowrisc_ip/prim/rtl/prim_esc_pkg.sv → ...or/lowrisc_ip/ip/prim/rtl/prim_esc_pkg.sv
diff --git a/.../lowrisc_ip/prim/rtl/prim_esc_receiver.sv → ...wrisc_ip/ip/prim/rtl/prim_esc_receiver.sv b/.../lowrisc_ip/prim/rtl/prim_esc_receiver.sv → ...wrisc_ip/ip/prim/rtl/prim_esc_receiver.sv
diff --git a/...or/lowrisc_ip/prim/rtl/prim_esc_sender.sv → ...lowrisc_ip/ip/prim/rtl/prim_esc_sender.sv b/...or/lowrisc_ip/prim/rtl/prim_esc_sender.sv → ...lowrisc_ip/ip/prim/rtl/prim_esc_sender.sv
diff --git a/...or/lowrisc_ip/prim/rtl/prim_fifo_async.sv → ...lowrisc_ip/ip/prim/rtl/prim_fifo_async.sv b/...or/lowrisc_ip/prim/rtl/prim_fifo_async.sv → ...lowrisc_ip/ip/prim/rtl/prim_fifo_async.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_fifo_sync.sv → .../lowrisc_ip/ip/prim/rtl/prim_fifo_sync.sv b/vendor/lowrisc_ip/prim/rtl/prim_fifo_sync.sv → .../lowrisc_ip/ip/prim/rtl/prim_fifo_sync.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_filter.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_filter.sv b/vendor/lowrisc_ip/prim/rtl/prim_filter.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_filter.sv
diff --git a/...or/lowrisc_ip/prim/rtl/prim_filter_ctr.sv → ...lowrisc_ip/ip/prim/rtl/prim_filter_ctr.sv b/...or/lowrisc_ip/prim/rtl/prim_filter_ctr.sv → ...lowrisc_ip/ip/prim/rtl/prim_filter_ctr.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_gate_gen.sv → ...r/lowrisc_ip/ip/prim/rtl/prim_gate_gen.sv b/vendor/lowrisc_ip/prim/rtl/prim_gate_gen.sv → ...r/lowrisc_ip/ip/prim/rtl/prim_gate_gen.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_gf_mult.sv → ...or/lowrisc_ip/ip/prim/rtl/prim_gf_mult.sv b/vendor/lowrisc_ip/prim/rtl/prim_gf_mult.sv → ...or/lowrisc_ip/ip/prim/rtl/prim_gf_mult.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_intr_hw.sv → ...or/lowrisc_ip/ip/prim/rtl/prim_intr_hw.sv b/vendor/lowrisc_ip/prim/rtl/prim_intr_hw.sv → ...or/lowrisc_ip/ip/prim/rtl/prim_intr_hw.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_keccak.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_keccak.sv b/vendor/lowrisc_ip/prim/rtl/prim_keccak.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_keccak.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_lfsr.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv b/vendor/lowrisc_ip/prim/rtl/prim_lfsr.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_packer.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_packer.sv b/vendor/lowrisc_ip/prim/rtl/prim_packer.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_packer.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_present.sv → ...or/lowrisc_ip/ip/prim/rtl/prim_present.sv b/vendor/lowrisc_ip/prim/rtl/prim_present.sv → ...or/lowrisc_ip/ip/prim/rtl/prim_present.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_prince.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_prince.sv b/vendor/lowrisc_ip/prim/rtl/prim_prince.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_prince.sv
diff --git a/...or/lowrisc_ip/prim/rtl/prim_pulse_sync.sv → ...lowrisc_ip/ip/prim/rtl/prim_pulse_sync.sv b/...or/lowrisc_ip/prim/rtl/prim_pulse_sync.sv → ...lowrisc_ip/ip/prim/rtl/prim_pulse_sync.sv
diff --git a/...or/lowrisc_ip/prim/rtl/prim_ram_1p_adv.sv → ...lowrisc_ip/ip/prim/rtl/prim_ram_1p_adv.sv b/...or/lowrisc_ip/prim/rtl/prim_ram_1p_adv.sv → ...lowrisc_ip/ip/prim/rtl/prim_ram_1p_adv.sv
diff --git a/...or/lowrisc_ip/prim/rtl/prim_ram_1p_scr.sv → ...lowrisc_ip/ip/prim/rtl/prim_ram_1p_scr.sv b/...or/lowrisc_ip/prim/rtl/prim_ram_1p_scr.sv → ...lowrisc_ip/ip/prim/rtl/prim_ram_1p_scr.sv
diff --git a/...or/lowrisc_ip/prim/rtl/prim_ram_2p_adv.sv → ...lowrisc_ip/ip/prim/rtl/prim_ram_2p_adv.sv b/...or/lowrisc_ip/prim/rtl/prim_ram_2p_adv.sv → ...lowrisc_ip/ip/prim/rtl/prim_ram_2p_adv.sv
diff --git a/...risc_ip/prim/rtl/prim_ram_2p_async_adv.sv → ...c_ip/ip/prim/rtl/prim_ram_2p_async_adv.sv b/...risc_ip/prim/rtl/prim_ram_2p_async_adv.sv → ...c_ip/ip/prim/rtl/prim_ram_2p_async_adv.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_rom_adv.sv → ...or/lowrisc_ip/ip/prim/rtl/prim_rom_adv.sv b/vendor/lowrisc_ip/prim/rtl/prim_rom_adv.sv → ...or/lowrisc_ip/ip/prim/rtl/prim_rom_adv.sv
diff --git a/...risc_ip/prim/rtl/prim_secded_28_22_dec.sv → ...c_ip/ip/prim/rtl/prim_secded_28_22_dec.sv b/...risc_ip/prim/rtl/prim_secded_28_22_dec.sv → ...c_ip/ip/prim/rtl/prim_secded_28_22_dec.sv
diff --git a/...risc_ip/prim/rtl/prim_secded_28_22_enc.sv → ...c_ip/ip/prim/rtl/prim_secded_28_22_enc.sv b/...risc_ip/prim/rtl/prim_secded_28_22_enc.sv → ...c_ip/ip/prim/rtl/prim_secded_28_22_enc.sv
diff --git a/...risc_ip/prim/rtl/prim_secded_39_32_dec.sv → ...c_ip/ip/prim/rtl/prim_secded_39_32_dec.sv b/...risc_ip/prim/rtl/prim_secded_39_32_dec.sv → ...c_ip/ip/prim/rtl/prim_secded_39_32_dec.sv
diff --git a/...risc_ip/prim/rtl/prim_secded_39_32_enc.sv → ...c_ip/ip/prim/rtl/prim_secded_39_32_enc.sv b/...risc_ip/prim/rtl/prim_secded_39_32_enc.sv → ...c_ip/ip/prim/rtl/prim_secded_39_32_enc.sv
diff --git a/...risc_ip/prim/rtl/prim_secded_72_64_dec.sv → ...c_ip/ip/prim/rtl/prim_secded_72_64_dec.sv b/...risc_ip/prim/rtl/prim_secded_72_64_dec.sv → ...c_ip/ip/prim/rtl/prim_secded_72_64_dec.sv
diff --git a/...risc_ip/prim/rtl/prim_secded_72_64_enc.sv → ...c_ip/ip/prim/rtl/prim_secded_72_64_enc.sv b/...risc_ip/prim/rtl/prim_secded_72_64_enc.sv → ...c_ip/ip/prim/rtl/prim_secded_72_64_enc.sv
diff --git a/.../lowrisc_ip/prim/rtl/prim_sram_arbiter.sv → ...wrisc_ip/ip/prim/rtl/prim_sram_arbiter.sv b/.../lowrisc_ip/prim/rtl/prim_sram_arbiter.sv → ...wrisc_ip/ip/prim/rtl/prim_sram_arbiter.sv
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_subreg.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_subreg.sv b/vendor/lowrisc_ip/prim/rtl/prim_subreg.sv → vendor/lowrisc_ip/ip/prim/rtl/prim_subreg.sv
diff --git a/...or/lowrisc_ip/prim/rtl/prim_subreg_arb.sv → ...lowrisc_ip/ip/prim/rtl/prim_subreg_arb.sv b/...or/lowrisc_ip/prim/rtl/prim_subreg_arb.sv → ...lowrisc_ip/ip/prim/rtl/prim_subreg_arb.sv
diff --git a/...or/lowrisc_ip/prim/rtl/prim_subreg_ext.sv → ...lowrisc_ip/ip/prim/rtl/prim_subreg_ext.sv b/...or/lowrisc_ip/prim/rtl/prim_subreg_ext.sv → ...lowrisc_ip/ip/prim/rtl/prim_subreg_ext.sv
diff --git a/...lowrisc_ip/prim/rtl/prim_subreg_shadow.sv → ...risc_ip/ip/prim/rtl/prim_subreg_shadow.sv b/...lowrisc_ip/prim/rtl/prim_subreg_shadow.sv → ...risc_ip/ip/prim/rtl/prim_subreg_shadow.sv
diff --git a/...or/lowrisc_ip/prim/rtl/prim_subst_perm.sv → ...lowrisc_ip/ip/prim/rtl/prim_subst_perm.sv b/...or/lowrisc_ip/prim/rtl/prim_subst_perm.sv → ...lowrisc_ip/ip/prim/rtl/prim_subst_perm.sv
diff --git a/...r/lowrisc_ip/prim/rtl/prim_sync_reqack.sv → ...owrisc_ip/ip/prim/rtl/prim_sync_reqack.sv b/...r/lowrisc_ip/prim/rtl/prim_sync_reqack.sv → ...owrisc_ip/ip/prim/rtl/prim_sync_reqack.sv
diff --git a/...lowrisc_ip/prim/rtl/prim_util_memload.svh → ...risc_ip/ip/prim/rtl/prim_util_memload.svh b/...lowrisc_ip/prim/rtl/prim_util_memload.svh → ...risc_ip/ip/prim/rtl/prim_util_memload.svh
diff --git a/vendor/lowrisc_ip/prim/rtl/prim_util_pkg.sv → ...r/lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv b/vendor/lowrisc_ip/prim/rtl/prim_util_pkg.sv → ...r/lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv
diff --git a/...r/lowrisc_ip/prim/util/get-lfsr-coeffs.py → ...owrisc_ip/ip/prim/util/get-lfsr-coeffs.py b/...r/lowrisc_ip/prim/util/get-lfsr-coeffs.py → ...owrisc_ip/ip/prim/util/get-lfsr-coeffs.py
diff --git a/vendor/lowrisc_ip/prim/util/keccak_rc.py → vendor/lowrisc_ip/ip/prim/util/keccak_rc.py b/vendor/lowrisc_ip/prim/util/keccak_rc.py → vendor/lowrisc_ip/ip/prim/util/keccak_rc.py
diff --git a/vendor/lowrisc_ip/prim/util/primgen.py → vendor/lowrisc_ip/ip/prim/util/primgen.py b/vendor/lowrisc_ip/prim/util/primgen.py → vendor/lowrisc_ip/ip/prim/util/primgen.py
diff --git a/...ip/prim/util/primgen/abstract_prim.sv.tpl → ...ip/prim/util/primgen/abstract_prim.sv.tpl b/...ip/prim/util/primgen/abstract_prim.sv.tpl → ...ip/prim/util/primgen/abstract_prim.sv.tpl
diff --git a/...sc_ip/prim/util/primgen/prim_pkg.core.tpl → ...ip/ip/prim/util/primgen/prim_pkg.core.tpl b/...sc_ip/prim/util/primgen/prim_pkg.core.tpl → ...ip/ip/prim/util/primgen/prim_pkg.core.tpl
diff --git a/...risc_ip/prim/util/primgen/prim_pkg.sv.tpl → ...c_ip/ip/prim/util/primgen/prim_pkg.sv.tpl b/...risc_ip/prim/util/primgen/prim_pkg.sv.tpl → ...c_ip/ip/prim/util/primgen/prim_pkg.sv.tpl
diff --git a/vendor/lowrisc_ip/prim/util/secded_gen.py → vendor/lowrisc_ip/ip/prim/util/secded_gen.py b/vendor/lowrisc_ip/prim/util/secded_gen.py → vendor/lowrisc_ip/ip/prim/util/secded_gen.py
diff --git a/...eneric/lint/prim_generic_clock_gating.vlt → ...eneric/lint/prim_generic_clock_gating.vlt b/...eneric/lint/prim_generic_clock_gating.vlt → ...eneric/lint/prim_generic_clock_gating.vlt
diff --git a/...ric/lint/prim_generic_clock_gating.waiver → ...ric/lint/prim_generic_clock_gating.waiver b/...ric/lint/prim_generic_clock_gating.waiver → ...ric/lint/prim_generic_clock_gating.waiver
diff --git a/..._generic/lint/prim_generic_clock_mux2.vlt → ..._generic/lint/prim_generic_clock_mux2.vlt b/..._generic/lint/prim_generic_clock_mux2.vlt → ..._generic/lint/prim_generic_clock_mux2.vlt
diff --git a/...neric/lint/prim_generic_clock_mux2.waiver → ...neric/lint/prim_generic_clock_mux2.waiver b/...neric/lint/prim_generic_clock_mux2.waiver → ...neric/lint/prim_generic_clock_mux2.waiver
diff --git a/.../prim_generic/lint/prim_generic_flash.vlt → .../prim_generic/lint/prim_generic_flash.vlt b/.../prim_generic/lint/prim_generic_flash.vlt → .../prim_generic/lint/prim_generic_flash.vlt
diff --git a/...im_generic/lint/prim_generic_flash.waiver → ...im_generic/lint/prim_generic_flash.waiver b/...im_generic/lint/prim_generic_flash.waiver → ...im_generic/lint/prim_generic_flash.waiver
diff --git a/...ip/prim_generic/lint/prim_generic_otp.vlt → ...ip/prim_generic/lint/prim_generic_otp.vlt b/...ip/prim_generic/lint/prim_generic_otp.vlt → ...ip/prim_generic/lint/prim_generic_otp.vlt
diff --git a/...prim_generic/lint/prim_generic_otp.waiver → ...prim_generic/lint/prim_generic_otp.waiver b/...prim_generic/lint/prim_generic_otp.waiver → ...prim_generic/lint/prim_generic_otp.waiver
diff --git a/...generic/lint/prim_generic_pad_wrapper.vlt → ...generic/lint/prim_generic_pad_wrapper.vlt b/...generic/lint/prim_generic_pad_wrapper.vlt → ...generic/lint/prim_generic_pad_wrapper.vlt
diff --git a/...eric/lint/prim_generic_pad_wrapper.waiver → ...eric/lint/prim_generic_pad_wrapper.waiver b/...eric/lint/prim_generic_pad_wrapper.waiver → ...eric/lint/prim_generic_pad_wrapper.waiver
diff --git a/...prim_generic/lint/prim_generic_ram_1p.vlt → ...prim_generic/lint/prim_generic_ram_1p.vlt b/...prim_generic/lint/prim_generic_ram_1p.vlt → ...prim_generic/lint/prim_generic_ram_1p.vlt
diff --git a/...m_generic/lint/prim_generic_ram_1p.waiver → ...m_generic/lint/prim_generic_ram_1p.waiver b/...m_generic/lint/prim_generic_ram_1p.waiver → ...m_generic/lint/prim_generic_ram_1p.waiver
diff --git a/...prim_generic/lint/prim_generic_ram_2p.vlt → ...prim_generic/lint/prim_generic_ram_2p.vlt b/...prim_generic/lint/prim_generic_ram_2p.vlt → ...prim_generic/lint/prim_generic_ram_2p.vlt
diff --git a/...m_generic/lint/prim_generic_ram_2p.waiver → ...m_generic/lint/prim_generic_ram_2p.waiver b/...m_generic/lint/prim_generic_ram_2p.waiver → ...m_generic/lint/prim_generic_ram_2p.waiver
diff --git a/...ip/prim_generic/lint/prim_generic_rom.vlt → ...ip/prim_generic/lint/prim_generic_rom.vlt b/...ip/prim_generic/lint/prim_generic_rom.vlt → ...ip/prim_generic/lint/prim_generic_rom.vlt
diff --git a/...prim_generic/lint/prim_generic_rom.waiver → ...prim_generic/lint/prim_generic_rom.waiver b/...prim_generic/lint/prim_generic_rom.waiver → ...prim_generic/lint/prim_generic_rom.waiver
diff --git a/.../prim_generic/prim_generic_clock_buf.core → .../prim_generic/prim_generic_clock_buf.core b/.../prim_generic/prim_generic_clock_buf.core → .../prim_generic/prim_generic_clock_buf.core
diff --git a/...im_generic/prim_generic_clock_gating.core → ...im_generic/prim_generic_clock_gating.core b/...im_generic/prim_generic_clock_gating.core → ...im_generic/prim_generic_clock_gating.core
diff --git a/.../prim_generic/prim_generic_clock_inv.core → .../prim_generic/prim_generic_clock_inv.core b/.../prim_generic/prim_generic_clock_inv.core → .../prim_generic/prim_generic_clock_inv.core
diff --git a/...prim_generic/prim_generic_clock_mux2.core → ...prim_generic/prim_generic_clock_mux2.core b/...prim_generic/prim_generic_clock_mux2.core → ...prim_generic/prim_generic_clock_mux2.core
diff --git a/...c_ip/prim_generic/prim_generic_flash.core → ...p/ip/prim_generic/prim_generic_flash.core b/...c_ip/prim_generic/prim_generic_flash.core → ...p/ip/prim_generic/prim_generic_flash.core
diff --git a/...sc_ip/prim_generic/prim_generic_flop.core → ...ip/ip/prim_generic/prim_generic_flop.core b/...sc_ip/prim_generic/prim_generic_flop.core → ...ip/ip/prim_generic/prim_generic_flop.core
diff --git a/...prim_generic/prim_generic_flop_2sync.core → ...prim_generic/prim_generic_flop_2sync.core b/...prim_generic/prim_generic_flop_2sync.core → ...prim_generic/prim_generic_flop_2sync.core
diff --git a/...isc_ip/prim_generic/prim_generic_otp.core → ..._ip/ip/prim_generic/prim_generic_otp.core b/...isc_ip/prim_generic/prim_generic_otp.core → ..._ip/ip/prim_generic/prim_generic_otp.core
diff --git a/...rim_generic/prim_generic_pad_wrapper.core → ...rim_generic/prim_generic_pad_wrapper.core b/...rim_generic/prim_generic_pad_wrapper.core → ...rim_generic/prim_generic_pad_wrapper.core
diff --git a/..._ip/prim_generic/prim_generic_ram_1p.core → .../ip/prim_generic/prim_generic_ram_1p.core b/..._ip/prim_generic/prim_generic_ram_1p.core → .../ip/prim_generic/prim_generic_ram_1p.core
diff --git a/..._ip/prim_generic/prim_generic_ram_2p.core → .../ip/prim_generic/prim_generic_ram_2p.core b/..._ip/prim_generic/prim_generic_ram_2p.core → .../ip/prim_generic/prim_generic_ram_2p.core
diff --git a/...isc_ip/prim_generic/prim_generic_rom.core → ..._ip/ip/prim_generic/prim_generic_rom.core b/...isc_ip/prim_generic/prim_generic_rom.core → ..._ip/ip/prim_generic/prim_generic_rom.core
diff --git a/...rim_generic/rtl/prim_generic_clock_buf.sv → ...rim_generic/rtl/prim_generic_clock_buf.sv b/...rim_generic/rtl/prim_generic_clock_buf.sv → ...rim_generic/rtl/prim_generic_clock_buf.sv
diff --git a/..._generic/rtl/prim_generic_clock_gating.sv → ..._generic/rtl/prim_generic_clock_gating.sv b/..._generic/rtl/prim_generic_clock_gating.sv → ..._generic/rtl/prim_generic_clock_gating.sv
diff --git a/...rim_generic/rtl/prim_generic_clock_inv.sv → ...rim_generic/rtl/prim_generic_clock_inv.sv b/...rim_generic/rtl/prim_generic_clock_inv.sv → ...rim_generic/rtl/prim_generic_clock_inv.sv
diff --git a/...im_generic/rtl/prim_generic_clock_mux2.sv → ...im_generic/rtl/prim_generic_clock_mux2.sv b/...im_generic/rtl/prim_generic_clock_mux2.sv → ...im_generic/rtl/prim_generic_clock_mux2.sv
diff --git a/...ip/prim_generic/rtl/prim_generic_flash.sv → ...ip/prim_generic/rtl/prim_generic_flash.sv b/...ip/prim_generic/rtl/prim_generic_flash.sv → ...ip/prim_generic/rtl/prim_generic_flash.sv
diff --git a/..._ip/prim_generic/rtl/prim_generic_flop.sv → .../ip/prim_generic/rtl/prim_generic_flop.sv b/..._ip/prim_generic/rtl/prim_generic_flop.sv → .../ip/prim_generic/rtl/prim_generic_flop.sv
diff --git a/...im_generic/rtl/prim_generic_flop_2sync.sv → ...im_generic/rtl/prim_generic_flop_2sync.sv b/...im_generic/rtl/prim_generic_flop_2sync.sv → ...im_generic/rtl/prim_generic_flop_2sync.sv
diff --git a/...c_ip/prim_generic/rtl/prim_generic_otp.sv → ...p/ip/prim_generic/rtl/prim_generic_otp.sv b/...c_ip/prim_generic/rtl/prim_generic_otp.sv → ...p/ip/prim_generic/rtl/prim_generic_otp.sv
diff --git a/...m_generic/rtl/prim_generic_pad_wrapper.sv → ...m_generic/rtl/prim_generic_pad_wrapper.sv b/...m_generic/rtl/prim_generic_pad_wrapper.sv → ...m_generic/rtl/prim_generic_pad_wrapper.sv
diff --git a/...p/prim_generic/rtl/prim_generic_ram_1p.sv → ...p/prim_generic/rtl/prim_generic_ram_1p.sv b/...p/prim_generic/rtl/prim_generic_ram_1p.sv → ...p/prim_generic/rtl/prim_generic_ram_1p.sv
diff --git a/...p/prim_generic/rtl/prim_generic_ram_2p.sv → ...p/prim_generic/rtl/prim_generic_ram_2p.sv b/...p/prim_generic/rtl/prim_generic_ram_2p.sv → ...p/prim_generic/rtl/prim_generic_ram_2p.sv
diff --git a/...c_ip/prim_generic/rtl/prim_generic_rom.sv → ...p/ip/prim_generic/rtl/prim_generic_rom.sv b/...c_ip/prim_generic/rtl/prim_generic_rom.sv → ...p/ip/prim_generic/rtl/prim_generic_rom.sv
diff --git a/..._xilinx/lint/prim_xilinx_clock_gating.vlt → ..._xilinx/lint/prim_xilinx_clock_gating.vlt b/..._xilinx/lint/prim_xilinx_clock_gating.vlt → ..._xilinx/lint/prim_xilinx_clock_gating.vlt
diff --git a/...linx/lint/prim_xilinx_clock_gating.waiver → ...linx/lint/prim_xilinx_clock_gating.waiver b/...linx/lint/prim_xilinx_clock_gating.waiver → ...linx/lint/prim_xilinx_clock_gating.waiver
diff --git a/...im_xilinx/lint/prim_xilinx_clock_mux2.vlt → ...im_xilinx/lint/prim_xilinx_clock_mux2.vlt b/...im_xilinx/lint/prim_xilinx_clock_mux2.vlt → ...im_xilinx/lint/prim_xilinx_clock_mux2.vlt
diff --git a/...xilinx/lint/prim_xilinx_clock_mux2.waiver → ...xilinx/lint/prim_xilinx_clock_mux2.waiver b/...xilinx/lint/prim_xilinx_clock_mux2.waiver → ...xilinx/lint/prim_xilinx_clock_mux2.waiver
diff --git a/...m_xilinx/lint/prim_xilinx_pad_wrapper.vlt → ...m_xilinx/lint/prim_xilinx_pad_wrapper.vlt b/...m_xilinx/lint/prim_xilinx_pad_wrapper.vlt → ...m_xilinx/lint/prim_xilinx_pad_wrapper.vlt
diff --git a/...ilinx/lint/prim_xilinx_pad_wrapper.waiver → ...ilinx/lint/prim_xilinx_pad_wrapper.waiver b/...ilinx/lint/prim_xilinx_pad_wrapper.waiver → ...ilinx/lint/prim_xilinx_pad_wrapper.waiver
diff --git a/...prim_xilinx/prim_xilinx_clock_gating.core → ...prim_xilinx/prim_xilinx_clock_gating.core b/...prim_xilinx/prim_xilinx_clock_gating.core → ...prim_xilinx/prim_xilinx_clock_gating.core
diff --git a/...p/prim_xilinx/prim_xilinx_clock_mux2.core → ...p/prim_xilinx/prim_xilinx_clock_mux2.core b/...p/prim_xilinx/prim_xilinx_clock_mux2.core → ...p/prim_xilinx/prim_xilinx_clock_mux2.core
diff --git a/.../prim_xilinx/prim_xilinx_pad_wrapper.core → .../prim_xilinx/prim_xilinx_pad_wrapper.core b/.../prim_xilinx/prim_xilinx_pad_wrapper.core → .../prim_xilinx/prim_xilinx_pad_wrapper.core
diff --git a/...im_xilinx/rtl/prim_xilinx_clock_gating.sv → ...im_xilinx/rtl/prim_xilinx_clock_gating.sv b/...im_xilinx/rtl/prim_xilinx_clock_gating.sv → ...im_xilinx/rtl/prim_xilinx_clock_gating.sv
diff --git a/...prim_xilinx/rtl/prim_xilinx_clock_mux2.sv → ...prim_xilinx/rtl/prim_xilinx_clock_mux2.sv b/...prim_xilinx/rtl/prim_xilinx_clock_mux2.sv → ...prim_xilinx/rtl/prim_xilinx_clock_mux2.sv
diff --git a/...rim_xilinx/rtl/prim_xilinx_pad_wrapper.sv → ...rim_xilinx/rtl/prim_xilinx_pad_wrapper.sv b/...rim_xilinx/rtl/prim_xilinx_pad_wrapper.sv → ...rim_xilinx/rtl/prim_xilinx_pad_wrapper.sv
diff --git a/vendor/lowrisc_ip/dvsim/Deploy.py → vendor/lowrisc_ip/util/dvsim/Deploy.py b/vendor/lowrisc_ip/dvsim/Deploy.py → vendor/lowrisc_ip/util/dvsim/Deploy.py
diff --git a/vendor/lowrisc_ip/dvsim/FlowCfg.py → vendor/lowrisc_ip/util/dvsim/FlowCfg.py b/vendor/lowrisc_ip/dvsim/FlowCfg.py → vendor/lowrisc_ip/util/dvsim/FlowCfg.py
diff --git a/vendor/lowrisc_ip/dvsim/FpvCfg.py → vendor/lowrisc_ip/util/dvsim/FpvCfg.py b/vendor/lowrisc_ip/dvsim/FpvCfg.py → vendor/lowrisc_ip/util/dvsim/FpvCfg.py
diff --git a/vendor/lowrisc_ip/dvsim/LintCfg.py → vendor/lowrisc_ip/util/dvsim/LintCfg.py b/vendor/lowrisc_ip/dvsim/LintCfg.py → vendor/lowrisc_ip/util/dvsim/LintCfg.py
diff --git a/vendor/lowrisc_ip/dvsim/Modes.py → vendor/lowrisc_ip/util/dvsim/Modes.py b/vendor/lowrisc_ip/dvsim/Modes.py → vendor/lowrisc_ip/util/dvsim/Modes.py
diff --git a/vendor/lowrisc_ip/dvsim/OneShotCfg.py → vendor/lowrisc_ip/util/dvsim/OneShotCfg.py b/vendor/lowrisc_ip/dvsim/OneShotCfg.py → vendor/lowrisc_ip/util/dvsim/OneShotCfg.py
diff --git a/vendor/lowrisc_ip/dvsim/SimCfg.py → vendor/lowrisc_ip/util/dvsim/SimCfg.py b/vendor/lowrisc_ip/dvsim/SimCfg.py → vendor/lowrisc_ip/util/dvsim/SimCfg.py
diff --git a/vendor/lowrisc_ip/dvsim/SynCfg.py → vendor/lowrisc_ip/util/dvsim/SynCfg.py b/vendor/lowrisc_ip/dvsim/SynCfg.py → vendor/lowrisc_ip/util/dvsim/SynCfg.py
diff --git a/vendor/lowrisc_ip/dvsim/__init__.py → vendor/lowrisc_ip/util/dvsim/__init__.py b/vendor/lowrisc_ip/dvsim/__init__.py → vendor/lowrisc_ip/util/dvsim/__init__.py
diff --git a/vendor/lowrisc_ip/dvsim/dvsim.py → vendor/lowrisc_ip/util/dvsim/dvsim.py b/vendor/lowrisc_ip/dvsim/dvsim.py → vendor/lowrisc_ip/util/dvsim/dvsim.py
diff --git a/vendor/lowrisc_ip/dvsim/sim_utils.py → vendor/lowrisc_ip/util/dvsim/sim_utils.py b/vendor/lowrisc_ip/dvsim/sim_utils.py → vendor/lowrisc_ip/util/dvsim/sim_utils.py
diff --git a/vendor/lowrisc_ip/dvsim/style.css → vendor/lowrisc_ip/util/dvsim/style.css b/vendor/lowrisc_ip/dvsim/style.css → vendor/lowrisc_ip/util/dvsim/style.css
diff --git a/vendor/lowrisc_ip/dvsim/testplanner.py → vendor/lowrisc_ip/util/dvsim/testplanner.py b/vendor/lowrisc_ip/dvsim/testplanner.py → vendor/lowrisc_ip/util/dvsim/testplanner.py
diff --git a/...or/lowrisc_ip/dvsim/testplanner/README.md → ...wrisc_ip/util/dvsim/testplanner/README.md b/...or/lowrisc_ip/dvsim/testplanner/README.md → ...wrisc_ip/util/dvsim/testplanner/README.md
diff --git a/.../lowrisc_ip/dvsim/testplanner/__init__.py → ...isc_ip/util/dvsim/testplanner/__init__.py b/.../lowrisc_ip/dvsim/testplanner/__init__.py → ...isc_ip/util/dvsim/testplanner/__init__.py
diff --git a/...owrisc_ip/dvsim/testplanner/class_defs.py → ...c_ip/util/dvsim/testplanner/class_defs.py b/...owrisc_ip/dvsim/testplanner/class_defs.py → ...c_ip/util/dvsim/testplanner/class_defs.py
diff --git a/...estplanner/examples/common_testplan.hjson → ...estplanner/examples/common_testplan.hjson b/...estplanner/examples/common_testplan.hjson → ...estplanner/examples/common_testplan.hjson
diff --git a/...dvsim/testplanner/examples/foo_dv_plan.md → ...dvsim/testplanner/examples/foo_dv_plan.md b/...dvsim/testplanner/examples/foo_dv_plan.md → ...dvsim/testplanner/examples/foo_dv_plan.md
diff --git a/...stplanner/examples/foo_regr_results.hjson → ...stplanner/examples/foo_regr_results.hjson b/...stplanner/examples/foo_regr_results.hjson → ...stplanner/examples/foo_regr_results.hjson
diff --git a/...m/testplanner/examples/foo_testplan.hjson → ...m/testplanner/examples/foo_testplan.hjson b/...m/testplanner/examples/foo_testplan.hjson → ...m/testplanner/examples/foo_testplan.hjson
diff --git a/...sc_ip/dvsim/testplanner/testplan_utils.py → .../util/dvsim/testplanner/testplan_utils.py b/...sc_ip/dvsim/testplanner/testplan_utils.py → .../util/dvsim/testplanner/testplan_utils.py
diff --git a/vendor/lowrisc_ip/dvsim/utils.py → vendor/lowrisc_ip/util/dvsim/utils.py b/vendor/lowrisc_ip/dvsim/utils.py → vendor/lowrisc_ip/util/dvsim/utils.py
diff --git a/vendor/lowrisc_ip/uvmdvgen/Makefile.tpl → vendor/lowrisc_ip/util/uvmdvgen/Makefile.tpl b/vendor/lowrisc_ip/uvmdvgen/Makefile.tpl → vendor/lowrisc_ip/util/uvmdvgen/Makefile.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/README.md → vendor/lowrisc_ip/util/uvmdvgen/README.md b/vendor/lowrisc_ip/uvmdvgen/README.md → vendor/lowrisc_ip/util/uvmdvgen/README.md
diff --git a/vendor/lowrisc_ip/uvmdvgen/README.md.tpl → ...or/lowrisc_ip/util/uvmdvgen/README.md.tpl b/vendor/lowrisc_ip/uvmdvgen/README.md.tpl → ...or/lowrisc_ip/util/uvmdvgen/README.md.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/__init__.py → vendor/lowrisc_ip/util/uvmdvgen/__init__.py b/vendor/lowrisc_ip/uvmdvgen/__init__.py → vendor/lowrisc_ip/util/uvmdvgen/__init__.py
diff --git a/vendor/lowrisc_ip/uvmdvgen/agent.core.tpl → ...r/lowrisc_ip/util/uvmdvgen/agent.core.tpl b/vendor/lowrisc_ip/uvmdvgen/agent.core.tpl → ...r/lowrisc_ip/util/uvmdvgen/agent.core.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/agent.sv.tpl → vendor/lowrisc_ip/util/uvmdvgen/agent.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/agent.sv.tpl → vendor/lowrisc_ip/util/uvmdvgen/agent.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/agent_cfg.sv.tpl → ...lowrisc_ip/util/uvmdvgen/agent_cfg.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/agent_cfg.sv.tpl → ...lowrisc_ip/util/uvmdvgen/agent_cfg.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/agent_cov.sv.tpl → ...lowrisc_ip/util/uvmdvgen/agent_cov.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/agent_cov.sv.tpl → ...lowrisc_ip/util/uvmdvgen/agent_cov.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/agent_pkg.sv.tpl → ...lowrisc_ip/util/uvmdvgen/agent_pkg.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/agent_pkg.sv.tpl → ...lowrisc_ip/util/uvmdvgen/agent_pkg.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/base_seq.sv.tpl → .../lowrisc_ip/util/uvmdvgen/base_seq.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/base_seq.sv.tpl → .../lowrisc_ip/util/uvmdvgen/base_seq.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/base_test.sv.tpl → ...lowrisc_ip/util/uvmdvgen/base_test.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/base_test.sv.tpl → ...lowrisc_ip/util/uvmdvgen/base_test.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/base_vseq.sv.tpl → ...lowrisc_ip/util/uvmdvgen/base_vseq.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/base_vseq.sv.tpl → ...lowrisc_ip/util/uvmdvgen/base_vseq.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/bind.sv.tpl → vendor/lowrisc_ip/util/uvmdvgen/bind.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/bind.sv.tpl → vendor/lowrisc_ip/util/uvmdvgen/bind.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/checklist.md.tpl → ...lowrisc_ip/util/uvmdvgen/checklist.md.tpl b/vendor/lowrisc_ip/uvmdvgen/checklist.md.tpl → ...lowrisc_ip/util/uvmdvgen/checklist.md.tpl
diff --git a/...or/lowrisc_ip/uvmdvgen/common_vseq.sv.tpl → ...wrisc_ip/util/uvmdvgen/common_vseq.sv.tpl b/...or/lowrisc_ip/uvmdvgen/common_vseq.sv.tpl → ...wrisc_ip/util/uvmdvgen/common_vseq.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/cov_excl.el.tpl → .../lowrisc_ip/util/uvmdvgen/cov_excl.el.tpl b/vendor/lowrisc_ip/uvmdvgen/cov_excl.el.tpl → .../lowrisc_ip/util/uvmdvgen/cov_excl.el.tpl
diff --git a/.../lowrisc_ip/uvmdvgen/device_driver.sv.tpl → ...isc_ip/util/uvmdvgen/device_driver.sv.tpl b/.../lowrisc_ip/uvmdvgen/device_driver.sv.tpl → ...isc_ip/util/uvmdvgen/device_driver.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/driver.sv.tpl → ...or/lowrisc_ip/util/uvmdvgen/driver.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/driver.sv.tpl → ...or/lowrisc_ip/util/uvmdvgen/driver.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/env.core.tpl → vendor/lowrisc_ip/util/uvmdvgen/env.core.tpl b/vendor/lowrisc_ip/uvmdvgen/env.core.tpl → vendor/lowrisc_ip/util/uvmdvgen/env.core.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/env.sv.tpl → vendor/lowrisc_ip/util/uvmdvgen/env.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/env.sv.tpl → vendor/lowrisc_ip/util/uvmdvgen/env.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/env_cfg.sv.tpl → ...r/lowrisc_ip/util/uvmdvgen/env_cfg.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/env_cfg.sv.tpl → ...r/lowrisc_ip/util/uvmdvgen/env_cfg.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/env_cov.sv.tpl → ...r/lowrisc_ip/util/uvmdvgen/env_cov.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/env_cov.sv.tpl → ...r/lowrisc_ip/util/uvmdvgen/env_cov.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/env_pkg.sv.tpl → ...r/lowrisc_ip/util/uvmdvgen/env_pkg.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/env_pkg.sv.tpl → ...r/lowrisc_ip/util/uvmdvgen/env_pkg.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/gen_agent.py → vendor/lowrisc_ip/util/uvmdvgen/gen_agent.py b/vendor/lowrisc_ip/uvmdvgen/gen_agent.py → vendor/lowrisc_ip/util/uvmdvgen/gen_agent.py
diff --git a/vendor/lowrisc_ip/uvmdvgen/gen_env.py → vendor/lowrisc_ip/util/uvmdvgen/gen_env.py b/vendor/lowrisc_ip/uvmdvgen/gen_env.py → vendor/lowrisc_ip/util/uvmdvgen/gen_env.py
diff --git a/...or/lowrisc_ip/uvmdvgen/host_driver.sv.tpl → ...wrisc_ip/util/uvmdvgen/host_driver.sv.tpl b/...or/lowrisc_ip/uvmdvgen/host_driver.sv.tpl → ...wrisc_ip/util/uvmdvgen/host_driver.sv.tpl
diff --git a/vendor/lowrisc_ip/uvmdvgen/if.sv.tpl → vendor/lowrisc_ip/util/uvmdvgen/if.sv.tpl b/vendor/lowrisc_ip/uvmdvgen/if.sv.tpl → vendor/lowrisc_ip/util/uvmdvgen/if.sv.tpl