Avoid spurious rebuilds in core_ibex Makefile with OUT = sim

We have an order-only dependency on the output directory in the rule
for $(sim-cfg-mk). If that output directory happens to be called
"sim", we now have a dependency on "sim". But that's the name of a
phony rule that runs the simulation, which means we end up doing stuff
in a strange order and defeating the variable dumping in the
dependency tracking, causing a spurious rebuild.

This patch defines a variable called OUT-DIR, which is OUT with a
trailing '/' appended. We use it uniformly in the rest of the file
but (I think) it's probably only actually needed in the dependency for
$(sim-cfg-mk). Now, the rule depends on "sim/", which isn't the name
of a phony rule, and all is well.

dv/uvm/core_ibex/Makefile

@@ -73,6 +73,12 @@ ifeq (${ISS},ovpsim)
 	ISS_OPTS += --override riscvOVPsim/cpu/PMP_grain=${PMP_GRANULARITY}
 endif
 
+# A version of $(OUT) with a trailing '/'. The point is that this will
+# never match the name of a phony targets like "sim" (which causes
+# strange rebuilds otherwise). The call to $(dir ) avoids adding
+# another trailing slash if $(OUT) had one already.
+OUT-DIR := $(dir $(OUT)/)
+
 # This expands to '@' if VERBOSE is 0 or not set, and to the empty
 # string otherwise. Prefix commands with it in order that they only
 # get printed when VERBOSE.
@@ -90,7 +96,7 @@ sim: post_compare cov
 
 .PHONY: clean
 clean:
-	rm -rf ${OUT}
+	rm -rf $(OUT-DIR)
 
 # Common options for all targets
 COMMON_OPTS := $(if $(call equal,$(VERBOSE),1),--verbose,)
@@ -119,14 +125,14 @@ metadata := $(OUT-SEED)/.metadata
 # targets. To ensure the directory has been built, add a order-only dependency
 # (with the pipe symbol before it) on the directory name and add the directory
 # to this list.
-gen-dirs := $(OUT) $(OUT-SEED) $(metadata) $(OUT)/rtl_sim
+gen-dirs := $(OUT-DIR) $(OUT-SEED) $(metadata) $(OUT-DIR)rtl_sim
 
 $(gen-dirs): %:
 	mkdir -p $@
 
 # sim-cfg-mk is a makefile fragment that sets-up anything simulator specific, it
 # is generated by sim_makefrag_gen.py
-sim-cfg-mk = $(OUT)/.sim-cfg.mk
+sim-cfg-mk = $(OUT-DIR).sim-cfg.mk
 
 # The include of $(sim-cfg-mk) below tells Make that it should ensure the file
 # exists. This rule tells Make how to build it. We also want to ensure it's
@@ -138,7 +144,7 @@ sim-cfg-mk = $(OUT)/.sim-cfg.mk
 # contents of $(sim-cfg-mk), we run the rule again. To avoid that, we check for
 # MAKE_RESTARTS, which is defined on re-runs. Phew!
 ifndef MAKE_RESTARTS
-$(sim-cfg-mk): FORCE | $(OUT)
+$(sim-cfg-mk): FORCE | $(OUT-DIR)
 	@./sim_makefrag_gen.py $(SIMULATOR) $(IBEX_CONFIG) $(PRJ_DIR) $@
 endif
 
@@ -331,7 +337,7 @@ all-verilog = \
   $(shell find ../.. -name '*.v' -o -name '*.sv' -o -name '*.svh')
 
 compile-var-deps := COMMON_OPTS SIMULATOR COV WAVES COMPILE_OPTS
--include $(OUT)/rtl_sim/.compile-vars.mk
+-include $(OUT-DIR)rtl_sim/.compile-vars.mk
 compile-vars-prereq = $(call vars-prereq,comp,compiling TB,$(compile-var-deps))
 
 $(call dump-vars-match,$(compile-var-deps),comp)
@@ -340,22 +346,22 @@ cov-arg := $(if $(call equal,$(COV),1),--en_cov,)
 wave-arg := $(if $(call equal,$(WAVES),1),--en_wave,)
 lsf-arg := $(if $(LSF_CMD),--lsf_cmd="$(LSF_CMD)",)
 
-$(OUT)/rtl_sim/.compile.stamp: \
+$(OUT-DIR)rtl_sim/.compile.stamp: \
   $(compile-vars-prereq) $(all-verilog) $(risc-dv-files) \
   sim.py yaml/rtl_simulation.yaml \
-  | $(OUT)/rtl_sim
+  | $(OUT-DIR)rtl_sim
 	$(verb)./sim.py \
-	 --o=${OUT} \
+	 --o=$(OUT-DIR) \
 	 --steps=compile \
 	 ${COMMON_OPTS} \
 	 --simulator="${SIMULATOR}" --simulator_yaml=yaml/rtl_simulation.yaml \
 	 $(cov-arg) $(wave-arg) $(lsf-arg) \
 	 --cmp_opts="${COMPILE_OPTS}"
-	$(call dump-vars,$(OUT)/rtl_sim/.compile-vars.mk,comp,$(compile-var-deps))
+	$(call dump-vars,$(OUT-DIR)rtl_sim/.compile-vars.mk,comp,$(compile-var-deps))
 	@touch $@
 
 .PHONY: compile
-compile: $(OUT)/rtl_sim/.compile.stamp
+compile: $(OUT-DIR)rtl_sim/.compile.stamp
 
 ###############################################################################
 # Run ibex RTL simulation with generated programs
@@ -369,9 +375,9 @@ compile: $(OUT)/rtl_sim/.compile.stamp
 # COV and WAVES, but these dependencies will come for free from the dependency
 # on the compiled TB.
 $(metadata)/rtl_sim.compile.stamp: \
-  $(gen-vars-prereq) $(risc-dv-files) $(OUT)/rtl_sim/.compile.stamp
+  $(gen-vars-prereq) $(risc-dv-files) $(OUT-DIR)rtl_sim/.compile.stamp
 	rm -rf $(OUT-SEED)/rtl_sim
-	cp -r $(OUT)/rtl_sim $(OUT-SEED)
+	cp -r $(OUT-DIR)rtl_sim $(OUT-SEED)
 	@touch $@
 
 # This rule actually runs the simulation. It depends on the copied-in testbench
@@ -421,13 +427,13 @@ fcov:
 
 # Merge all output coverage directories into the <out>/rtl_sim directory
 cov:
-	$(verb)rm -rf ${OUT}/rtl_sim/test.vdb
+	$(verb)rm -rf $(OUT-DIR)rtl_sim/test.vdb
 	$(verb)./sim.py \
 		--steps=cov \
 		${TEST_OPTS} \
 		--simulator="${SIMULATOR}" \
 		$(lsf-arg) \
-		--o="${OUT}"
+		--o="$(OUT-DIR)"
 	@if [ -d "test.vdb" ]; then \
-		mv -f test.vdb ${OUT}/rtl_sim/; \
+		mv -f test.vdb $(OUT-DIR)rtl_sim/; \
 	fi