Update lowrisc_ip to lowRISC/opentitan@7aa5c2b89

Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7aa5c2b890fa5d4e3d0b43e0f5e561cb7743a01d * [flash] updated flash wrapper md file (Dana Agur) * [flash / top / ast] functional updates (Timothy Chen) * [ralgen, dv] Associated changes to ralgen (Srikrishna Iyer) * [prim_sync_reqack_data] Fix SVA checking DST-to-SRC data stability (Pirmin Vogel) * [dv/keymgr] temp disable alert checking in scb (Cindy Chen) * [dvsim] Fix a wrong path in print message (Weicai Yang) * [prim] Teach verilator to recognise a clock gate (Rupert Swarbrick) * [prim_lc_sync] Add AsyncOn parameter to enable/disable the sync flops (Michael Schaffner) * [clkmgr / top] Add clock divider step down to support lc_ctrl transition (Timothy Chen) * [prim_sync_reqack] Use NRZ protocol internally for increased throughput (Pirmin Vogel) * [prim] correct interface documentation. (Timothy Chen) * [flash_ctrl] Add tlul configuration interface to prim_flash (Timothy Chen) * [flash_ctrl] Use hamming code for 64b ECC (Timothy Chen) * [prim/edn] Fix lint error (width mismatch) (Eunchan Kim) Signed-off-by: Greg Chadwick <[email protected]>
mithro · Jan 22, 2021 · d717e23 · d717e23
1 parent 698cf93
commit d717e23
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diff --git a/vendor/lowrisc_ip.lock.hjson b/vendor/lowrisc_ip.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowRISC/opentitan
-    rev: 7e131447da6d5f3044666a17974e15df44f0328b
+    rev: 7aa5c2b890fa5d4e3d0b43e0f5e561cb7743a01d
   }
 }
diff --git a/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh b/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh
@@ -539,4 +539,23 @@
   end
 `endif
 
+// Creates a SVA cover that can be used in a covergroup.
+//
+// This macro creates an unnamed SVA cover from the expression `__sva` and an event with the name
+// `__ev_name`. When the SVA cover is hit, the event is triggered. A coverpoint can cover the
+// `triggered` property of the event.
+`ifndef DV_FCOV_SVA
+`define DV_FCOV_SVA(__ev_name, __sva, __clk = clk_i, __rst = rst_ni) \
+  event __ev_name; \
+  cover property (@(posedge __clk) disable iff (__rst == 0) (__sva)) begin \
+    -> __ev_name; \
+  end
+`endif
+
+// Creates a coverpoint for an expression where only the expression true case is of interest for
+// coverage (e.g. where the expression indicates an event has occured).
+`ifndef DV_FCOV_EXPR_SEEN
+`define DV_FCOV_EXPR_SEEN(__cp_name, __expr) __cp_name: coverpoint __expr { bins seen = {1}; }
+`endif
+
 `endif // __DV_MACROS_SVH__
diff --git a/vendor/lowrisc_ip/dv/tools/ralgen/README.md b/vendor/lowrisc_ip/dv/tools/ralgen/README.md
@@ -15,6 +15,10 @@ The adjoining `ralgen.core` file registers the `ralgen` generator. The FuseSoC
 core file that 'calls' the generator adds it as a dependency. When calling the
 generator, the following parameters are set:
 * **name (mandatory)**: Name of the RAL package (typically, same is the IP).
+* **dv_base_prefix (optional)**: The prefix added to the base classes from
+  which the register classes are derived. Set this option to derive the register
+  classes not from the default `dv_base_reg`, but from user defined custom
+  class definitions.
 * **ip_hjson**: Path to the hjson specification written for an IP which includes
   the register descriptions. This needs to be a valid input for `reggen`.
 * **top_hjson**: Path to the hjson specification for a top level design. This
@@ -30,7 +34,9 @@ generate:
     generator: ralgen
     parameters:
       name: <name>
-      <ip_hjson|top_hjson>: <path-to-hjson-spec>
+      ip_hjson|top_hjson: <path-to-hjson-spec>
+      [dv_base_prefix: my_base]
+
 
 targets:
   default:
@@ -63,11 +69,15 @@ the `name` parameter to derive the
 [VLNV](https://fusesoc.readthedocs.io/en/master/user/overview.html#core-naming-rules)
 name for the generated core file.
 
-The generated core file adds **`lowrisc:dv:dv_lib`** as a dependency for the
-generated RAL package. This is required because our DV register block, register
-and field models are derived from the
+The generated core file adds **`lowrisc:dv:dv_base_reg`** as a dependency for
+the generated RAL package. This is required because our DV register block,
+register and field models are derived from the
 [DV library]({{< relref "hw/dv/sv/dv_lib/README.md" >}}) of classes. This
-ensures the right compilation order is maintained.
+ensures the right compilation order is maintained. If the `dv_base_prefix`
+argument is set, then it adds **`lowrisc:dv:my_base_reg`** as an extra
+dependency, where `my_base` is the value of the argument as shown in the
+example above. This core file and the associated sources are assumed to be
+available in the provided FuseSoC search paths.
 
 ## Limitations
 

diff --git a/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.py b/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.py
@@ -49,6 +49,7 @@ def main():
     name = gapi['parameters'].get('name')
     ip_hjson = gapi['parameters'].get('ip_hjson')
     top_hjson = gapi['parameters'].get('top_hjson')
+    dv_base_prefix = gapi['parameters'].get('dv_base_prefix')
     if not name or (bool(ip_hjson) == bool(top_hjson)):
         print("Error: ralgen requires the \"name\" and exactly one of "
               "{\"ip_hjson\" and \"top_hjson\"} parameters to be set.")
@@ -65,6 +66,11 @@ def main():
         cmd = os.path.join(util_path, "topgen.py")
         args = [cmd, "-r", "-o", ".", "-t", ral_spec]
 
+    depends = ["lowrisc:dv:dv_base_reg"]
+    if dv_base_prefix and dv_base_prefix != "dv_base":
+        args.extend(["--dv-base-prefix", dv_base_prefix])
+        depends.append("lowrisc:dv:{}_reg".format(dv_base_prefix))
+
     try:
         subprocess.run(args, check=True)
     except subprocess.CalledProcessError as e:
@@ -77,9 +83,7 @@ def main():
         'name': "lowrisc:dv:{}_ral_pkg".format(name),
         'filesets': {
             'files_dv': {
-                'depend': [
-                    "lowrisc:dv:dv_base_reg",
-                ],
+                'depend': depends,
                 'files': [
                     ral_pkg_file,
                 ],

diff --git a/vendor/lowrisc_ip/ip/prim/doc/prim_flash.md b/vendor/lowrisc_ip/ip/prim/doc/prim_flash.md
@@ -38,14 +38,21 @@ tck_i                   | input  | jtag tck
 tdi_i                   | input  | jtag tdi
 tms_i                   | input  | jtag tms
 tdo_o                   | output | jtag tdo
+bist_enable_i           | input  | lc_ctrl_pkg :: On for bist_enable input
 scanmode_i              | input  | dft scanmode input
+scan_en_i               | input  | dft scan shift input
 scan_rst_n_i            | input  | dft scanmode reset
-flash_power_ready_h_io  | inout  | flash power is ready (high voltage connection)
-flash_power_down_h_io   | inout  | flash wrapper is powering down (high voltage connection)
-flash_test_mode_a_io    | inout  | flash test mode values (analog connection)
-flash_test_voltage_h_io | inout  | flash test mode voltage (high voltage connection)
-
-
+flash_power_ready_h_i   | input  | flash power is ready (high voltage connection)
+flash_power_down_h_i    | input  | flash wrapper is powering down (high voltage connection)
+flash_test_mode_a_i     | input  | flash test mode values (analog connection)
+flash_test_voltage_h_i  | input  | flash test mode voltage (high voltage connection)
+flash_err_o             | output | flash level error interrupt indication, cleared on write 1 to status register
+flash_alert_po          | output | flash positive detector alert 
+flash_alert_no          | output | flash negative detector alert 
+flash_alert_ack         | input  | single pulse ack
+flash_alert_trig        | input  | alert force trig by SW
+tl_i                    | input  | TL_UL  interface for rd/wr registers access
+tl_o                    | output | TL_UL  interface for rd/wr registers access
 ### Flash Request/Response Signals
 
 Name               | In/Out | Description
@@ -60,12 +67,12 @@ erase_suspend      | input  | erase suspend request
 addr               | input  | requested transaction address
 part               | input  | requested transaction partition
 info_sel           | input  | if requested transaction is information partition, the type of information partition accessed
-he                 | output | high endurance enable for requested address
+he                 | input  | high endurance enable for requested address
 prog_data          | input  | program data
 ack                | output | transction acknowledge
 rd_data            | output | transaction read data
 done               | output | transaction done
-erase_suspend_done | output | erase suspend done
+
 
 
 # Theory of Operations
@@ -81,18 +88,18 @@ Depending on the type of transaction, there may be a significant gap between `ac
 For example, a read may have only 1 or 2 cycles between transaction acknowledgement and transaction complete.
 Whereas a program or erase may have a gap extending up to uS or even mS.
 
-It is the flash wrapper's decision on how many outstanding transaction to accept.
+It is the flash wrapper decision on how many outstanding transaction to accept.
 The following are examples for read, program and erase transactions.
 
 ### Read
 {{< wavejson >}}
 {signal: [
-  {name: 'clk_i',     wave: 'p................'},
-  {name: 'rd_i',      wave: '011..0.1..0......'},
-  {name: 'addr_i',    wave: 'x22..x.2..x......'},
-  {name: 'ack_o',     wave: '1.0.10...10......'},
-  {name: 'done_o',    wave: '0...10...10....10'},
-  {name: 'rd_data_o', wave: 'x...2x...2x....2x'},
+  {name: 'clk_i',     wave: 'p.................'},
+  {name: 'rd_i',      wave: '011..0.1..0.......'},
+  {name: 'addr_i',    wave: 'x22..x.2..x.......'},
+  {name: 'ack_o',     wave: '010.10...10.......'},
+  {name: 'done_o',    wave: '0....10...10....10'},
+  {name: 'rd_data_o', wave: 'x....2x...2x....2x'},
 ]}
 {{< /wavejson >}}
 
@@ -141,17 +148,22 @@ A program type not supported by the wrapper, indicated through `prog_type_avail`
 
 ## Erase Suspend
 Since erase operations can take a significant amount of time, sometimes it is necessary for software or other components to suspend the operation.
-The suspend operation follows a similar request (`erase_suspend_req` and done (`erase_suspend_done`) interface.
+The suspend operation input request starts with `erase_suspend_req` assertion. Flash wrapper circuit acks when wrapper starts suspend. 
 When the erase suspend completes, the flash wrapper circuitry also asserts `done` for the ongoing erase transaction to ensure all hardware gracefully completes.
 
 The following is an example diagram
 {{< wavejson >}}
 {signal: [
   {name: 'clk_i',                wave: 'p................'},
-  {name: 'pg_erase_i',           wave: '01............0..'},
-  {name: 'ack_o',                wave: '1.0..............'},
-  {name: 'erase_suspend_i',      wave: '0.....1.......0..'},
+  {name: 'pg_erase_i',           wave: '01.0..............'},
+  {name: 'ack_o',                wave: '0.10...10........'},
+  {name: 'erase_suspend_i',      wave: '0.....1.0........'},
   {name: 'done_o',               wave: '0............10..'},
-  {name: 'erase_suspend_done_o', wave: '0............10..'},
-]}
+ ]
+  }
 {{< /wavejson >}}
+
+## Error Interrupt
+The `flash_err_o` is a level interrupt indication, that is asserted whenever an error event occurs in one of the Flash banks.
+An Error status register is used to hold the error source of both banks, and it is cleared on writing 1 to the relevant bit.
+Clearing the status register trigs deassertion of the interrupt.
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_div.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_div.waiver
@@ -3,3 +3,6 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # waiver file for prim_clock_div
+
+waive -rules DUAL_EDGE_CLOCK -location {prim_clock_div.sv} -regexp {.*} \
+      -comment "The clock switch signal is synchronized on negative edge to ensure it is away from any transition"
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/rtl/prim_sync_reqack_tb.sv b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/rtl/prim_sync_reqack_tb.sv
@@ -57,7 +57,8 @@ module prim_sync_reqack_tb #(
   logic rst_done;
 
   // Instantiate DUT
-  logic [WidthTrans-1:0] out_data, unused_out_data;
+  logic [WidthTrans-1:0] in_data, out_data, unused_out_data;
+  assign in_data = DataSrc2Dst ? src_count_q : dst_count_q;
   prim_sync_reqack_data #(
     .Width       ( WidthTrans  ),
     .DataSrc2Dst ( DataSrc2Dst ),
@@ -73,7 +74,7 @@ module prim_sync_reqack_tb #(
     .dst_req_o  (dst_req),
     .dst_ack_i  (dst_ack),
 
-    .data_i (dst_count_q),
+    .data_i (in_data),
     .data_o (out_data)
   );
   assign unused_out_data = out_data;

diff --git a/vendor/lowrisc_ip/ip/prim/prim_clock_div.core b/vendor/lowrisc_ip/ip/prim/prim_clock_div.core
@@ -16,7 +16,16 @@ filesets:
       - rtl/prim_clock_div.sv
     file_type: systemVerilogSource
 
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_clock_div.waiver
+    file_type: waiver
+
 targets:
   default:
     filesets:
+      - tool_ascentlint ? (files_ascentlint_waiver)
       - files_rtl
diff --git a/vendor/lowrisc_ip/ip/prim/prim_secded.core b/vendor/lowrisc_ip/ip/prim/prim_secded.core
@@ -16,6 +16,8 @@ filesets:
       - rtl/prim_secded_39_32_enc.sv
       - rtl/prim_secded_72_64_dec.sv
       - rtl/prim_secded_72_64_enc.sv
+      - rtl/prim_secded_hamming_72_64_dec.sv
+      - rtl/prim_secded_hamming_72_64_enc.sv
     file_type: systemVerilogSource
 
 targets:

diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_div.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_div.sv
@@ -10,11 +10,17 @@ module prim_clock_div #(
 ) (
   input clk_i,
   input rst_ni,
+  input step_down_req_i, // step down divisor by 2x
+  output logic step_down_ack_o, // step down acknowledge
   input test_en_i,
   output logic clk_o
 );
 
 
+  // Only even divide is supported at the moment
+  // For odd divide we need to introduce more parameters to control duty cycle
+  `ASSERT_INIT(DivEven_A, (Divisor % 2) == 0)
+
   logic clk_int;
 
   if (Divisor == 2) begin : gen_div2
@@ -38,28 +44,56 @@ module prim_clock_div #(
       .clk_no(q_n)
     );
 
-    assign clk_int = q_p;
+    logic step_down_nq;
+    always_ff @(negedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+        step_down_nq <= 1'b0;
+      end else begin
+        step_down_nq <= step_down_req_i;
+      end
+    end
+
+    // make sure selection point is away from both edges
+    prim_clock_mux2 #(
+      .NoFpgaBufG(1'b1)
+    ) u_step_down_mux (
+      .clk0_i(q_p),
+      .clk1_i(clk_i),
+      .sel_i(step_down_nq),
+      .clk_o(clk_int)
+    );
+
+  assign step_down_ack_o = step_down_nq;
 
   end else begin : gen_div
-    // Only even divide is supported at the moment
-    // For odd divide we need to introduce more parameters to control duty cycle
-    `ASSERT_INIT(DivEven_A, (Divisor % 2) == 0)
 
     localparam int ToggleCnt = Divisor / 2;
     localparam int CntWidth = $clog2(ToggleCnt);
     logic [CntWidth-1:0] cnt;
+    logic [CntWidth-1:0] limit;
+
+    assign limit = !step_down_req_i     ? ToggleCnt - 1 :
+                   (ToggleCnt / 2) == 2 ? '0 : (ToggleCnt / 2) - 1;
 
     always_ff @(posedge clk_i or negedge rst_ni) begin
       if (!rst_ni) begin
         cnt <= '0;
         clk_int <= ResetValue;
-      end else if (cnt == ToggleCnt-1) begin
+      end else if (cnt >= limit) begin
         cnt <= '0;
         clk_int <= ~clk_o;
       end else begin
         cnt <= cnt + 1'b1;
       end
     end
+
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+        step_down_ack_o <= 1'b0;
+      end else begin
+        step_down_ack_o <= step_down_req_i;
+      end
+    end
   end
 
   // when in scanmode, bypass the dividers completely

diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_edn_req.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_edn_req.sv
@@ -38,8 +38,9 @@ module prim_edn_req
 
   logic [edn_pkg::ENDPOINT_BUS_WIDTH-1:0] word_data;
   logic word_fips;
+  localparam int SyncWidth = $bits({edn_i.edn_fips, edn_i.edn_bus});
   prim_sync_reqack_data #(
-    .Width(edn_pkg::ENDPOINT_BUS_WIDTH),
+    .Width(SyncWidth),
     .DataSrc2Dst(1'b0),
     .DataReg(1'b0)
   ) u_prim_sync_reqack_data (

diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sync.sv
@@ -15,7 +15,11 @@ module prim_lc_sync #(
   // The buffer cells have a don't touch constraint
   // on them such that synthesis tools won't collapse
   // all copies into one signal.
-  parameter int NumCopies = 1
+  parameter int NumCopies = 1,
+  // This instantiates the synchronizer flops if set to 1.
+  // In special cases where the receiver is in the same clock domain as the sender,
+  // this can be set to 0. However, it is recommended to leave this at 1.
+  parameter bit AsyncOn = 1
 ) (
   input                                       clk_i,
   input                                       rst_ni,
@@ -26,15 +30,19 @@ module prim_lc_sync #(
   `ASSERT_INIT(NumCopiesMustBeGreaterZero_A, NumCopies > 0)
 
   logic [lc_ctrl_pkg::TxWidth-1:0] lc_en;
-  prim_flop_2sync #(
-    .Width(lc_ctrl_pkg::TxWidth),
-    .ResetValue(lc_ctrl_pkg::TxWidth'(lc_ctrl_pkg::Off))
-  ) u_prim_flop_2sync (
-    .clk_i,
-    .rst_ni,
-    .d_i(lc_en_i),
-    .q_o(lc_en)
-  );
+  if (AsyncOn) begin : gen_flops
+    prim_flop_2sync #(
+      .Width(lc_ctrl_pkg::TxWidth),
+      .ResetValue(lc_ctrl_pkg::TxWidth'(lc_ctrl_pkg::Off))
+    ) u_prim_flop_2sync (
+      .clk_i,
+      .rst_ni,
+      .d_i(lc_en_i),
+      .q_o(lc_en)
+    );
+  end else begin : gen_no_flops
+    assign lc_en = lc_en_i;
+  end
 
   for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
     logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;