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  1. graph-generation graph-generation Public

    Forked from JiaxuanYou/graph-generation

    GraphRNN: Generating Realistic Graphs with Deep Auto-regressive Models

    Python

  2. circuit2graph circuit2graph Public

    Forked from circuitgraph/circuitgraph

    Tools for working with circuits as graphs in python

    Verilog

  3. LOSTIN-GNN-priedict-synthesis- LOSTIN-GNN-priedict-synthesis- Public

    Forked from lydiawunan/LOSTIN

    LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models

    Verilog

  4. OpenABC OpenABC Public

    Forked from NYU-MLDA/OpenABC

    OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

    Jupyter Notebook

  5. LSOracle--logic-synthesis-generate-framework LSOracle--logic-synthesis-generate-framework Public

    Forked from lnis-uofu/LSOracle

    IDEA project source files

    Verilog

  6. Developing-Synthesis-Flows-Without-Human-Knowledge Developing-Synthesis-Flows-Without-Human-Knowledge Public

    Forked from ycunxi/FLowGen-CNNs-DAC18

    Jupyter Notebook