Linux kernel privilege escalation techniques

The Unified TileLink Memory Subsystem Tester for XiangShan

Repository containing all SeSa paper online appendices

RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System

Binary service written in C played at the international CTF Enowars 8

OpenXuantie - OpenC910 Core

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

32-bit Superscalar RISC-V CPU

Recursive MMIO VM Escape PoC

Write-ups for various CTF

DIG is a numerical invariant generation tool. It infers program invariants or properties over (i) program execution traces or (ii) program source code. DIG supports many forms of numerical invarian…

A simple superscalar out-of-order RISC-V microprocessor

A collection of links related to Linux kernel security and exploitation

GEF - GDB Enhanced Features for exploit devs & reversers

Transient Execution EMulator

Open-source high-performance RISC-V processor

a new class of file structure attacks

Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)

SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs (ICCAD 2023)

Direct Memory Access (DMA) Attack Software

Working draft of nextgen malloc implementation for musl libc

UBGen can generate programs with undefined behaviors (e.g., buffer-overflow, use-after-free, etc.)

CVE-2021-3156 - Sudo Baron Samedit

Exploit Development and Reverse Engineering with GDB & LLDB Made Easy

Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

Collect crash (or UndefinedBehaviorSanitizer error) reports, triage, and estimate severity.