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Achievement: QuickdrawAchievement: YOLOAchievement: Pull Sharkx2

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@efabless

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  • openlane2 Public

    Forked from efabless/openlane2

    The next generation of OpenLane, rewritten from scratch with a modular architecture

    Python Apache License 2.0 Updated Aug 7, 2024

  • IP_Utilities Public

    Forked from shalan/IP_Utilities

    AUC Open Hardware Lab (AUCOHL) IP Utilities

    Python Apache License 2.0 Updated Aug 6, 2024

  • timer Public

    Verilog Apache License 2.0 Updated Aug 6, 2023

  • caravel_ram Public

    Verilog Apache License 2.0 Updated Aug 3, 2023

  • LDO Public

    Tcl Apache License 2.0 Updated May 2, 2023

  • OpenLane Public

    Forked from The-OpenROAD-Project/OpenLane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Verilog Apache License 2.0 Updated Mar 21, 2023

  • caravel_mgmt_soc_gf180mcu Public

    Forked from efabless/caravel_mgmt_soc_gf180mcu

    This repository is the GF180MCU port of management core for Caravel. For more information about the Caravel management SoC, see https://github.com/efabless/caravel_mgmt_soc_litex.

    Verilog Apache License 2.0 Updated Nov 20, 2022

  • caravel-gf180mcu Public

    Forked from efabless/caravel-gf180mcu

    This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.

    Verilog Apache License 2.0 Updated Nov 17, 2022

  • Caravel-off-the-flow-OpenLane-scripts Public

    Tcl Updated Nov 3, 2022

  • caravel Public

    Forked from efabless/caravel

    Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

    Verilog Apache License 2.0 Updated Oct 17, 2022

  • gpio_control_block Public

    Implementation of the gpio_control_block for Caravel

    Verilog Updated Sep 27, 2022

  • mpc-1 Public

    Forked from efabless/caravel_mini

    Multi-Project Support for Caravel

    Verilog Apache License 2.0 Updated Sep 18, 2022

  • Extended-ARM Public

    Added a global predictor with index sharing to the ARM pipelined processor rtl from Harris & Harris textbook.

    SystemVerilog Updated Sep 6, 2022

  • uvm_enviroment Public

    UVM environment for Scrambler module verification

    SystemVerilog Updated Sep 6, 2022