Renode - Antmicro's virtual development framework for complex embedded systems

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

SystemVerilog compiler and language services

Verible provides a SystemVerilog parser, style-linter, and formatter.

a small build system with a focus on speed

An example of how to use Clang's LibTooling interface.

A modeling library with virtual components for SystemC and TLM simulators

Tutorials & examples for Arm software development tools.

pysdr.org textbook source material, feel free to post issues/PRs

Yosys Open SYnthesis Suite

Pandoc Template for creating Trivadis CI like documentation.

C library for Convolutional codes and Reed-Solomon

Verilog AXI components for FPGA implementation

Verilog AXI stream components for FPGA implementation

A book for learning the Vim editor

Vim syntax highlighting based on the bat CLI tool

ABC: System for Sequential Logic Synthesis and Formal Verification

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

OpenSTA engine

SystemVerilog to Verilog conversion