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Swift community driven package for OpenAI public API
Get up and running with Llama 3.3, DeepSeek-R1, Phi-4, Gemma 3, and other large language models.
Staggeringly powerful macOS desktop automation with Lua
FPGA im action for the board Sipeed TangNano 20K
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
4 stage, in-order, compute RISC-V core based on the CV32E40P
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
A secure embedded operating system for microcontrollers
The multi-core cluster of a PULP system.
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
Verilog AXI components for FPGA implementation
A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
RT-Thread is an open source IoT Real-Time Operating System (RTOS).
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Official Repository of "Capacity Info". Link to Google Play:
A command-line tool and Xcode Extension for formatting Swift code
Small footprint and configurable DRAM core
Format text book to html formatted with page separation
An alternative crate registry, implemented in Rust.