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OpenTitan: Open source silicon root of trust

SystemVerilog 2,679 809 Updated Feb 11, 2025

Ariane is a 6-stage RISC-V CPU

SystemVerilog 1 Updated May 31, 2019

The OpenPiton Platform

Assembly 1 1 Updated Jun 6, 2019

lowRISC Style Guides

1 Updated Feb 11, 2020

Package manager and build abstraction tool for FPGA/ASIC development

Python 1 Updated Apr 17, 2020

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

SystemVerilog 1 Updated Jan 19, 2024

An abstraction library for interfacing EDA tools

Python 1 Updated Aug 8, 2020

OpenTitan: Open source silicon root of trust

SystemVerilog 1 1 Updated Mar 19, 2024

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,466 571 Updated Jan 24, 2025

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

SystemVerilog 453 120 Updated Oct 23, 2024

RISC-V Cores, SoC platforms and SoCs

857 208 Updated Mar 26, 2021

A MATLAB toolbox for exporting publication quality figures

MATLAB 1,293 369 Updated Nov 5, 2024

Classic multiplayer tetris for the terminal

C 219 31 Updated Feb 8, 2025

CVA6 SDK containing RISC-V tools and Buildroot

Makefile 61 68 Updated Jun 22, 2024

The OpenPiton Platform

Assembly 666 217 Updated Oct 11, 2024