Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

arch/arm/cpu/armv7/exynos/Kconfig

@@ -18,6 +18,9 @@ config TARGET_ORIGEN
 config TARGET_TRATS2
 	bool "Exynos4412 Trat2 board"
 
+config TARGET_ODROID
+	bool "Exynos4412 Odroid board"
+
 config TARGET_ARNDALE
 	bool "Exynos5250 Arndale board"
 
@@ -48,6 +51,7 @@ source "board/samsung/trats/Kconfig"
 source "board/samsung/universal_c210/Kconfig"
 source "board/samsung/origen/Kconfig"
 source "board/samsung/trats2/Kconfig"
+source "board/samsung/odroid/Kconfig"
 source "board/samsung/arndale/Kconfig"
 source "board/samsung/smdk5250/Kconfig"
 source "board/samsung/smdk5420/Kconfig"

arch/arm/cpu/armv7/exynos/clock.c

@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 	 * VPLL_CON: MIDV [24:16]
 	 * BPLL_CON: MIDV [25:16]: Exynos5
 	 */
-	if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+	if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+	    pllreg == SPLL)
 		mask = 0x3ff;
 	else
 		mask = 0x1ff;
@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
 		r = readl(&clk->rpll_con0);
 		k = readl(&clk->rpll_con1);
 		break;
+	case SPLL:
+		r = readl(&clk->spll_con0);
+		break;
 	default:
 		printf("Unsupported PLL (%d)\n", pllreg);
 		return 0;
@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
 	return pclk;
 }
 
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_DISP10
+	 * FIMD1_SEL [4]
+	 * 0: SCLK_RPLL
+	 * 1: SCLK_SPLL
+	 */
+	sel = readl(&clk->src_disp10);
+	sel &= (1 << 4);
+
+	if (sel)
+		sclk = get_pll_clk(SPLL);
+	else
+		sclk = get_pll_clk(RPLL);
+
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_disp10);
+	ratio = ratio & 0xf;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
 void exynos4_set_lcd_clk(void)
 {
 	struct exynos4_clock *clk =
@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
 	clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
 }
 
+void exynos5420_set_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned int cfg;
+
+	/*
+	 * CLK_SRC_DISP10
+	 * FIMD1_SEL [4]
+	 * 0: SCLK_RPLL
+	 * 1: SCLK_SPLL
+	 */
+	cfg = readl(&clk->src_disp10);
+	cfg &= ~(0x1 << 4);
+	cfg |= (0 << 4);
+	writel(cfg, &clk->src_disp10);
+
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO		[3:0]
+	 */
+	cfg = readl(&clk->div_disp10);
+	cfg &= ~(0xf << 0);
+	cfg |= (0 << 0);
+	writel(cfg, &clk->div_disp10);
+}
+
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =
@@ -1602,16 +1667,24 @@ unsigned long get_lcd_clk(void)
 {
 	if (cpu_is_exynos4())
 		return exynos4_get_lcd_clk();
-	else
-		return exynos5_get_lcd_clk();
+	else {
+		if (proid_is_exynos5420())
+			return exynos5420_get_lcd_clk();
+		else
+			return exynos5_get_lcd_clk();
+	}
 }
 
 void set_lcd_clk(void)
 {
 	if (cpu_is_exynos4())
 		exynos4_set_lcd_clk();
-	else
-		exynos5_set_lcd_clk();
+	else {
+		if (proid_is_exynos5250())
+			exynos5_set_lcd_clk();
+		else if (proid_is_exynos5420())
+			exynos5420_set_lcd_clk();
+	}
 }
 
 void set_mipi_clk(void)

arch/arm/cpu/armv7/exynos/clock_init.h

@@ -75,6 +75,9 @@ struct mem_timings {
 	unsigned spll_mdiv;
 	unsigned spll_pdiv;
 	unsigned spll_sdiv;
+	unsigned rpll_mdiv;
+	unsigned rpll_pdiv;
+	unsigned rpll_sdiv;
 	unsigned pclk_cdrex_ratio;
 	unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
 

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c

@@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = {
 		.spll_mdiv = 0xc8,
 		.spll_pdiv = 0x3,
 		.spll_sdiv = 0x2,
+		/* RPLL @70.5Mhz */
+		.rpll_mdiv = 0x5E,
+		.rpll_pdiv = 0x2,
+		.rpll_sdiv = 0x4,
 
 		.direct_cmd_msr = {
 			0x00020018, 0x00030000, 0x00010046, 0x00000d70,
@@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void)
 	writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
 	writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
 	writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+	writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
 
 	setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
 
@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void)
 	while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
 		;
 
+	/* Set RPLL */
+	writel(RPLL_CON2_VAL, &clk->rpll_con2);
+	writel(RPLL_CON1_VAL, &clk->rpll_con1);
+	val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
+	writel(val, &clk->rpll_con0);
+	while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
+		;
+
 	writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
 	writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
 

arch/arm/cpu/armv7/exynos/exynos5_setup.h

@@ -783,7 +783,7 @@
 #define CLK_SRC_TOP2_VAL	0x11101000
 #define CLK_SRC_TOP3_VAL	0x11111111
 #define CLK_SRC_TOP4_VAL	0x11110111
-#define CLK_SRC_TOP5_VAL	0x11111100
+#define CLK_SRC_TOP5_VAL	0x11111101
 #define CLK_SRC_TOP6_VAL	0x11110111
 #define CLK_SRC_TOP7_VAL	0x00022200
 

arch/arm/cpu/armv7/exynos/pinmux.c

@@ -704,8 +704,8 @@ static int exynos4x12_mmc_config(int peripheral, int flags)
 		ext_func = S5P_GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC4:
-		start = EXYNOS4_GPIO_K00;
-		start_ext = EXYNOS4_GPIO_K13;
+		start = EXYNOS4X12_GPIO_K00;
+		start_ext = EXYNOS4X12_GPIO_K13;
 		func = S5P_GPIO_FUNC(0x3);
 		ext_func = S5P_GPIO_FUNC(0x4);
 		break;

arch/arm/cpu/armv7/exynos/power.c

@@ -202,3 +202,10 @@ void power_exit_wakeup(void)
 	else
 		exynos4_power_exit_wakeup();
 }
+
+unsigned int get_boot_mode(void)
+{
+	unsigned int om_pin = samsung_get_base_power();
+
+	return readl(om_pin) & OM_PIN_MASK;
+}

arch/arm/cpu/armv7/exynos/spl_boot.c

@@ -20,7 +20,6 @@
 #include "clock_init.h"
 
 DECLARE_GLOBAL_DATA_PTR;
-#define OM_STAT         (0x1f << 1)
 
 /* Index into irom ptr table */
 enum index {
@@ -184,7 +183,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
 */
 void copy_uboot_to_ram(void)
 {
-	enum boot_mode bootmode = BOOT_MODE_OM;
+	unsigned int bootmode = BOOT_MODE_OM;
 
 	u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
 	u32 offset = 0, size = 0;
@@ -207,7 +206,7 @@ void copy_uboot_to_ram(void)
 #endif
 
 	if (bootmode == BOOT_MODE_OM)
-		bootmode = readl(samsung_get_base_power()) & OM_STAT;
+		bootmode = get_boot_mode();
 
 	switch (bootmode) {
 #ifdef CONFIG_SPI_BOOTING
@@ -216,7 +215,7 @@ void copy_uboot_to_ram(void)
 		exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
 		break;
 #endif
-	case BOOT_MODE_MMC:
+	case BOOT_MODE_SD:
 		offset = BL2_START_OFFSET;
 		size = BL2_SIZE_BLOC_COUNT;
 		copy_bl2 = get_irom_func(MMC_INDEX);

arch/arm/dts/Makefile

@@ -1,7 +1,8 @@
 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
 	exynos4210-universal_c210.dtb \
 	exynos4210-trats.dtb \
-	exynos4412-trats2.dtb
+	exynos4412-trats2.dtb \
+	exynos4412-odroid.dtb
 
 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-snow.dtb \

arch/arm/dts/exynos4412-odroid.dts

@@ -0,0 +1,70 @@
+/*
+ * Odroid-U3/X2 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+	model = "Odroid based on Exynos4412";
+	compatible = "samsung,odroid", "samsung,exynos4412";
+
+	aliases {
+		i2c0 = "/i2c@13860000";
+		serial0 = "/serial@13800000";
+		console = "/serial@13810000";
+		mmc2 = "sdhci@12530000";
+		mmc4 = "dwmmc@12550000";
+	};
+
+	i2c@13860000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-slave-addr = <0x10>;
+		samsung,i2c-max-bus-freq = <100000>;
+		status = "okay";
+
+		max77686_pmic@09 {
+			compatible = "maxim,max77686_pmic";
+			interrupts = <7 0>;
+			reg = <0x09 0 0>;
+			#clock-cells = <1>;
+		};
+	};
+
+	serial@13810000 {
+		status = "okay";
+	};
+
+	sdhci@12510000 {
+		status = "disabled";
+	};
+
+	sdhci@12520000 {
+		status = "disabled";
+	};
+
+	sdhci@12530000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		cd-gpios = <&gpio 0xC2 0>;
+	};
+
+	sdhci@12540000 {
+		status = "disabled";
+	};
+
+	dwmmc@12550000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <2 1 0>;
+		samsung,removable = <0>;
+		fifoth_val = <0x203f0040>;
+		bus_hz = <400000000>;
+		div = <0x3>;
+		index = <4>;
+	};
+};

arch/arm/dts/exynos5420-peach-pit.dts

@@ -63,6 +63,11 @@
 	              reg = <0x20>;
 	              compatible = "maxim,max98090-codec";
 	       };
+
+	        edp-lvds-bridge@48 {
+	                compatible = "parade,ps8625";
+	                reg = <0x48>;
+	        };
 	};
 
         sound@3830000 {
@@ -124,4 +129,29 @@
 	xhci@12400000 {
 		samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
 	};
+
+	fimd@14400000 {
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <1366>;
+		samsung,vl-row = <768>;
+		samsung,vl-width = <1366>;
+		samsung,vl-height = <768>;
+
+		samsung,vl-clkp;
+		samsung,vl-dp;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <32>;
+		samsung,vl-hbpd = <40>;
+		samsung,vl-hfpd = <40>;
+		samsung,vl-vspw = <6>;
+		samsung,vl-vbpd = <10>;
+		samsung,vl-vfpd = <12>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,winid = <3>;
+		samsung,interface-mode = <1>;
+		samsung,dp-enabled = <1>;
+		samsung,dual-lcd-enabled = <0>;
+	};
 };

arch/arm/dts/exynos54xx.dtsi

@@ -113,6 +113,16 @@
 		status = "disabled";
 	};
 
+	fimdm0_sysmmu@0x14640000 {
+		compatible = "samsung,sysmmu-v3.3";
+		reg = <0x14640000 0x100>;
+	};
+
+	fimdm1_sysmmu@0x14680000 {
+		compatible = "samsung,sysmmu-v3.3";
+		reg = <0x14680000 0x100>;
+	};
+
 	fimd@14400000 {
 		/* sysmmu is not used in U-Boot */
 		samsung,disable-sysmmu;

arch/arm/include/asm/arch-exynos/clk.h

@@ -15,6 +15,7 @@
 #define VPLL	4
 #define BPLL	5
 #define RPLL	6
+#define SPLL	7
 
 #define MASK_PRE_RATIO(x)	(0xff << ((x << 4) + 8))
 #define MASK_RATIO(x)		(0xf << (x << 4))