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sbuffer: use plru replacement policy (OpenXiangShan#622)
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* sbuffer: use plru

* sbuffer: use drainIdx when drain sbuffer

* Fix typo

* sbuffer: set the evict threshold=12

Co-authored-by: ljw <[email protected]>
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@fwzhang @ljwljwljwljw
fwzhang and ljwljwljwljw authored Mar 3, 2021
1 parent d7bc15b commit 1aad9ee
Showing 1 changed file with 30 additions and 73 deletions.
103 changes: 30 additions & 73 deletions src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -49,71 +49,6 @@ class SbufferLine extends SbufferBundle {
}
}

class ChooseReplace(nWay: Int) extends XSModule {
val io = IO(new Bundle{
val mask = Vec(nWay, Input(Bool()))
val way = Output(UInt(nWay.W))
val flush = Input(Bool())
})
val wayReg = RegInit(0.U(log2Up(nWay).W))
val wayMask = ~((UIntToOH(wayReg)<<1.U)(nWay-1,0) - 1.U)
val stateMask = Cat(io.mask.reverse)
val loMask = (wayMask & stateMask)(nWay-1,0)

val nextWay = PriorityEncoder(Cat(stateMask, loMask))(log2Up(nWay)-1, 0)
XSDebug(p"nextWay[${nextWay}]\n")

wayReg := nextWay
io.way := wayReg

when(io.flush){
wayReg := 0.U
}
}

class SbufferLru(nWay: Int) extends XSModule {
val io = IO(new Bundle{
val in = Vec(StorePipelineWidth, Input(UInt(nWay.W)))
val mask = Vec(StoreBufferSize, Input(Bool()))
val way = Output(UInt(nWay.W))
val flush = Input(Bool())
})

val lruRect = RegInit(VecInit(Seq.fill(StoreBufferSize)(0.U(nWay.W))))
val count = RegInit(VecInit(Seq.fill(StoreBufferSize)(0.U(log2Up(nWay+1).W))))
val idx = RegInit(VecInit(Seq.tabulate(StoreBufferSize)(i => i.U)))

//update
val updataMask = ParallelOR(io.in)
val updateValue = (~updataMask).asUInt()
for(i <- 0 until nWay){
val lruUpdate = Mux(updataMask(i), updateValue, lruRect(i) & updateValue)
lruRect(i) := lruUpdate
count(i) := PopCount(lruUpdate)
}

// get evictionIdx
val maskCount = Wire(Vec(StoreBufferSize, UInt((log2Up(1 + nWay) + log2Up(nWay)).W))) // (popcount, Idx)
val countZipIdx = maskCount.zip((0 until nWay).map(_.U))
for(i <- 0 until nWay){
val value = Mux(io.mask(i), count(i), nWay.U)
maskCount(i) := Cat(value, idx(i))
}

io.way := ParallelMin(maskCount)(log2Up(nWay)-1,0)

// flush
when(io.flush){
for(i <- 0 until nWay){
lruRect(i) := 0.U
count(i) := nWay.U
}
XSDebug("drain sbuffer finish, flush lru\n")
}
}



class NewSbuffer extends XSModule with HasSbufferConst {
val io = IO(new Bundle() {
val in = Vec(StorePipelineWidth, Flipped(Decoupled(new DCacheWordReq))) //Todo: store logic only support Width == 2 now
Expand Down Expand Up @@ -170,10 +105,21 @@ class NewSbuffer extends XSModule with HasSbufferConst {
val validCount = RegInit(0.U((log2Up(StoreBufferSize) + 1).W))
val full = invalidCount === 0.U // full = TODO: validCount(log2Up(StoreBufferSize))

val lru = Module(new ChooseReplace(StoreBufferSize))
val evictionIdx = lru.io.way
val plru = new PseudoLRU(StoreBufferSize)
val accessIdx = Wire(Vec(StorePipelineWidth + 1, Valid(UInt(SbufferIndexWidth.W))))
for (i <- 0 until StorePipelineWidth+1) {
accessIdx(i).valid := false.B
accessIdx(i).bits := 0.U
}

val replaceIdx = plru.way
plru.access(accessIdx)


val validMask = stateVec.map(s => isValid(s))
val drainIdx = PriorityEncoder(validMask)

lru.io.mask := stateVec.map(isValid(_))
val evictionIdx = Mux(sbuffer_state === x_drain_sbuffer, drainIdx, replaceIdx)

val intags = io.in.map(in => getTag(in.bits.addr))
val sameTag = intags(0) === intags(1)
Expand All @@ -196,9 +142,9 @@ class NewSbuffer extends XSModule with HasSbufferConst {
// insert confition
// firstInsert: the first invalid entry
// if first entry canMerge or second entry has the same tag with the first entry , secondInsert equal the first invalid entry, otherwise, the second invalid entry
val invalidMask = stateVec.map(s => isInvalid(s))
val evenInvalidMask = GetEvenBits(VecInit(invalidMask).asUInt)
val oddInvalidMask = GetOddBits(VecInit(invalidMask).asUInt)
val invalidMask = VecInit(stateVec.map(s => isInvalid(s)))
val evenInvalidMask = GetEvenBits(invalidMask.asUInt)
val oddInvalidMask = GetOddBits(invalidMask.asUInt)

val (evenRawInsertIdx, evenCanInsert) = PriorityEncoderWithFlag(evenInvalidMask)
val (oddRawInsertIdx, oddCanInsert) = PriorityEncoderWithFlag(oddInvalidMask)
Expand Down Expand Up @@ -255,12 +201,18 @@ class NewSbuffer extends XSModule with HasSbufferConst {
}
}

for (i <- 0 until StorePipelineWidth) {
accessIdx(i).valid := RegNext(io.in(i).fire())
}

// first store
when(io.in(0).fire()){
when(canMerge(0)){
accessIdx(0).bits := RegNext(mergeIdx(0))
mergeWordReq(io.in(0).bits, mergeIdx(0), firstWord)
XSDebug(p"merge req 0 to line [${mergeIdx(0)}]\n")
}.otherwise{
accessIdx(0).bits := RegNext(firstInsertIdx)
wordReqToBufLine(io.in(0).bits, intags(0), firstInsertIdx, firstWord, true.B)
XSDebug(p"insert req 0 to line[$firstInsertIdx]\n")
}
Expand All @@ -269,14 +221,19 @@ class NewSbuffer extends XSModule with HasSbufferConst {
// second store
when(io.in(1).fire()){
when(canMerge(1)){
accessIdx(1).bits := RegNext(mergeIdx(1))
mergeWordReq(io.in(1).bits, mergeIdx(1), secondWord)
XSDebug(p"merge req 1 to line [${mergeIdx(1)}]\n")
}.otherwise{
accessIdx(1).bits := RegNext(secondInsertIdx)
wordReqToBufLine(io.in(1).bits, intags(1), secondInsertIdx, secondWord, !sameTag)
XSDebug(p"insert req 1 to line[$secondInsertIdx]\n")
}
}

accessIdx.last.valid := invalidMask(replaceIdx)
accessIdx.last.bits := replaceIdx

for(i <- 0 until StoreBufferSize){
XSDebug(stateVec(i)=/=s_invalid,
p"[$i] timeout:${cohCount(i)(countBits-1)} state:${stateVec(i)}\n"
Expand All @@ -295,7 +252,6 @@ class NewSbuffer extends XSModule with HasSbufferConst {
)
}


// ---------------------- Send Dcache Req ---------------------

val do_eviction = Wire(Bool())
Expand All @@ -304,7 +260,7 @@ class NewSbuffer extends XSModule with HasSbufferConst {
do_eviction := validCount >= 12.U

io.flush.empty := RegNext(empty && io.sqempty)
lru.io.flush := sbuffer_state === x_drain_sbuffer && empty
// lru.io.flush := sbuffer_state === x_drain_sbuffer && empty
switch(sbuffer_state){
is(x_idle){
when(io.flush.valid){
Expand Down Expand Up @@ -354,6 +310,7 @@ class NewSbuffer extends XSModule with HasSbufferConst {
isValid(stateVec(evictionIdx)) &&
noSameBlockInflight(evictionIdx)


when(prepareValid){
stateVec(evictionIdx) := s_prepare
}
Expand Down

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