PASS coremark and microbench but loader(fence.i) FAIL

mwp1990 · Oct 30, 2020 · b7959e5 · b7959e5
1 parent 6f763b2
commit b7959e5
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/debug/Makefile b/debug/Makefile
@@ -3,7 +3,7 @@ NANOS_HOME ?= $(AM_HOME)/../nanos-lite
 SINGLETEST = ALL=min3
 
 B ?= 0
-E ?= 0
+E ?= -1
 V ?= OFF
 #V ?= OFF
 EMU_ARGS = B=$(B) E=$(E) V=$(V)
@@ -13,8 +13,7 @@ EMU_ARGS = B=$(B) E=$(E) V=$(V)
 # ------------------------------------------------------------------
 
 cache:
-	$(MAKE) -C $(AM_HOME)/tests/cachetest $(ARCH) ALL=loader $(EMU_ARGS) run 
-	#2>&1 | tee > loader.log
+	$(MAKE) -C $(AM_HOME)/tests/cachetest $(ARCH) ALL=loader $(EMU_ARGS) run 2>&1 | tee > loader.log
 	#2>&1 | tee > loader.log
 
 cpu:

diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala
@@ -291,7 +291,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter
 
   icache.io.mem_acquire <> l1pluscache.io.req
   l1pluscache.io.resp <> icache.io.mem_grant
-  l1pluscache.io.flush := false.B
+  l1pluscache.io.flush := icache.io.l1plusflush
 
   mem.io.backend   <> backend.io.mem
 

diff --git a/src/main/scala/xiangshan/cache/icache.scala b/src/main/scala/xiangshan/cache/icache.scala
@@ -90,6 +90,7 @@ class ICacheIO extends ICacheBundle
   val mem_grant   = Flipped(DecoupledIO(new L1plusCacheResp))
   val tlb = new BlockTlbRequestIO
   val flush = Input(UInt(2.W))
+  val l1plusflush = Output(Bool())
 }
 
 /* ------------------------------------------------------------
@@ -246,8 +247,6 @@ class ICache extends ICacheModule
   val outPacket =  Wire(UInt((FetchWidth * 32).W))
   outPacket := cutHelper(VecInit(dataHitWay),s3_req_pc(5,1).asUInt,s3_req_mask.asUInt)
 
-  val waitForRefillDone = cacheflushed
-
   //ICache MissQueue
   val icacheMissQueue = Module(new IcacheMissQueue)
   val blocking = RegInit(false.B)
@@ -348,6 +347,8 @@ class ICache extends ICacheModule
   io.mem_acquire <> icacheMissQueue.io.mem_acquire
   icacheMissQueue.io.mem_grant <> io.mem_grant
 
+  io.l1plusflush := icacheFlush
+
   XSDebug("[flush] flush_0:%d  flush_1:%d\n",io.flush(0),io.flush(1))
 
   //Performance Counter