DCacheLoadIO: delete s1_data for data is reponsed in s2 now

mwp1990 · Mar 3, 2021 · f9cda23 · f9cda23
1 parent f615fb4
commit f9cda23
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Showing 2 changed files with 0 additions and 14 deletions.
diff --git a/src/main/scala/xiangshan/cache/DCacheWrapper.scala b/src/main/scala/xiangshan/cache/DCacheWrapper.scala
@@ -82,17 +82,6 @@ class DCacheWordIO extends DCacheBundle
 
 // used by load unit
 class DCacheLoadIO extends DCacheWordIO
-{
-  // kill previous cycle's req
-  val s1_kill  = Output(Bool())
-  // cycle 0: virtual address: req.addr
-  // cycle 1: physical address: s1_paddr
-  val s1_paddr = Output(UInt(PAddrBits.W))
-  val s1_data  = Input(Vec(nWays, UInt(DataBits.W)))
-  val s2_hit_way = Input(UInt(nWays.W))
-}
-
-class NewDCacheLoadIO extends DCacheWordIO
 {
   // kill previous cycle's req
   val s1_kill  = Output(Bool())

diff --git a/src/main/scala/xiangshan/cache/LoadPipe.scala b/src/main/scala/xiangshan/cache/LoadPipe.scala
@@ -9,7 +9,6 @@ import utils.XSDebug
 class LoadPipe extends DCacheModule {
   val io = IO(new DCacheBundle {
     // incoming requests
-    // val lsu       = Flipped(new NewDCacheLoadIO)
     val lsu = Flipped(new DCacheLoadIO)
     // req got nacked in stage 0?
     val nack      = Input(Bool())
@@ -95,8 +94,6 @@ class LoadPipe extends DCacheModule {
   // only needs to read the specific row
   data_read.rmask := UIntToOH(get_row(s1_addr))
   io.data_read.valid := s1_fire && !s1_nack
-
-  io.lsu.s1_data := DontCare
 
   io.replace_access.valid := RegNext(io.meta_read.fire()) && s1_tag_match && s1_valid
   io.replace_access.bits.set := get_idx(s1_req.addr)