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Dongpo Li says: ==================== Add Hisilicon MDIO bus driver and FEMAC driver This patch set adds a Hisilicon MDIO bus driver and a Fast Ethernet MAC(FEMAC) driver. We also abstract a general interface "of_phy_get_and_connect" for PHY connect. User will have no bother with getting "phy-mode" and "phy-handle" any more. Changes in v1: - Pass private data structure instead of struct mii_bus in MDIO read and write operation. - Return the error which devm_clk_get() gives when MDIO probe. - Leave the clock unprepared and disabled on error when MDIO probe. - Abstract a general interface "of_phy_get_and_connect" for PHY connect. - Remove the "_reset" suffixes in "reset-names" property. - Enable tx per-packet interrupt when tx fifo full. - Remove pointless compatible and add SoC specific compatible. - Declare only one clock in MAC dts documentation. - Add standard unit suffixes for "phy-reset-delays". - Use a smaller NAPI poll weight 16 for our Fast Ethernet MAC. - Use phy_ethtool_{get|set}_link_ksettings for ethtool ops. - Use phydev from struct net_device in MAC driver. ==================== Signed-off-by: David S. Miller <[email protected]>
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Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt
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Hisilicon Fast Ethernet MDIO Controller interface | ||
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Required properties: | ||
- compatible: should be "hisilicon,hisi-femac-mdio". | ||
- reg: address and length of the register set for the device. | ||
- clocks: A phandle to the reference clock for this device. | ||
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- PHY subnode: inherits from phy binding [1] | ||
[1] Documentation/devicetree/bindings/net/phy.txt | ||
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Example: | ||
mdio: mdio@10091100 { | ||
compatible = "hisilicon,hisi-femac-mdio"; | ||
reg = <0x10091100 0x10>; | ||
clocks = <&crg HI3516CV300_MDIO_CLK>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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phy0: phy@1 { | ||
reg = <1>; | ||
}; | ||
}; |
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Hisilicon Fast Ethernet MAC controller | ||
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Required properties: | ||
- compatible: should contain one of the following version strings: | ||
* "hisilicon,hisi-femac-v1" | ||
* "hisilicon,hisi-femac-v2" | ||
and the soc string "hisilicon,hi3516cv300-femac". | ||
- reg: specifies base physical address(s) and size of the device registers. | ||
The first region is the MAC core register base and size. | ||
The second region is the global MAC control register. | ||
- interrupts: should contain the MAC interrupt. | ||
- clocks: A phandle to the MAC main clock. | ||
- resets: should contain the phandle to the MAC reset signal(required) and | ||
the PHY reset signal(optional). | ||
- reset-names: should contain the reset signal name "mac"(required) | ||
and "phy"(optional). | ||
- mac-address: see ethernet.txt [1]. | ||
- phy-mode: see ethernet.txt [1]. | ||
- phy-handle: see ethernet.txt [1]. | ||
- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given. | ||
The 1st cell is reset pre-delay in micro seconds. | ||
The 2nd cell is reset pulse in micro seconds. | ||
The 3rd cell is reset post-delay in micro seconds. | ||
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[1] Documentation/devicetree/bindings/net/ethernet.txt | ||
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Example: | ||
hisi_femac: ethernet@10090000 { | ||
compatible = "hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2"; | ||
reg = <0x10090000 0x1000>,<0x10091300 0x200>; | ||
interrupts = <12>; | ||
clocks = <&crg HI3518EV200_ETH_CLK>; | ||
resets = <&crg 0xec 0>,<&crg 0xec 3>; | ||
reset-names = "mac","phy"; | ||
mac-address = [00 00 00 00 00 00]; | ||
phy-mode = "mii"; | ||
phy-handle = <&phy0>; | ||
hisilicon,phy-reset-delays-us = <10000 20000 20000>; | ||
}; |
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