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care about depth_view
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@zfchu
zfchu committed Nov 2, 2020
1 parent ccc6adb commit 693a2ca
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Showing 3 changed files with 44 additions and 86 deletions.
38 changes: 15 additions & 23 deletions src/commands/cutrw.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,14 +37,6 @@ namespace alice
add_flag( "--xag_npn_lut,-g", "cut rewriting based on xag_npn_lut" );
add_flag( "--xag_npn,-p", "cut rewriting based on xag_npn" );
}

template<class Ntk>
void print_stats( const Ntk& ntk )
{
depth_view depth_ntk{ ntk };
std::cout << fmt::format( "ntk i/o = {}/{} gates = {} level = {}\n",
ntk.num_pis(), ntk.num_pos(), ntk.num_gates(), depth_ntk.depth() );
}

void execute()
{
Expand All @@ -53,7 +45,7 @@ namespace alice
{
m5ig_network m5ig = store<m5ig_network>().current();

print_stats( m5ig );
also::print_stats( m5ig );

/******************************************************/
/* for testing cut enumeration for m5ig */
Expand Down Expand Up @@ -96,7 +88,7 @@ namespace alice
m5ig = cut_rewriting( m5ig, resyn, ps );
m5ig = cleanup_dangling( m5ig );

print_stats( m5ig );
also::print_stats( m5ig );

store<m5ig_network>().extend();
store<m5ig_network>().current() = m5ig;
Expand All @@ -105,15 +97,15 @@ namespace alice
{
mig_network mig = store<mig_network>().current();

print_stats( mig );
also::print_stats( mig );

mig_npn_resynthesis resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
mig = cut_rewriting( mig, resyn, ps );
mig = cleanup_dangling( mig );

print_stats( mig );
also::print_stats( mig );

store<mig_network>().extend();
store<mig_network>().current() = mig;
Expand All @@ -122,7 +114,7 @@ namespace alice
{
xag_network xag = store<xag_network>().current();

print_stats( xag );
also::print_stats( xag );

xag_npn_lut_resynthesis resyn;
cut_rewriting_params ps;
Expand All @@ -137,7 +129,7 @@ namespace alice

xag = cleanup_dangling( xag );

print_stats( xag );
also::print_stats( xag );

store<xag_network>().extend();
store<xag_network>().current() = xag;
Expand All @@ -146,7 +138,7 @@ namespace alice
{
xag_network xag = store<xag_network>().current();

print_stats( xag );
also::print_stats( xag );

xag_npn_resynthesis<xag_network> resyn;
cut_rewriting_params ps;
Expand All @@ -156,7 +148,7 @@ namespace alice
cut_rewriting( xag, resyn, ps );
xag = cleanup_dangling( xag );

print_stats( xag );
also::print_stats( xag );

store<xag_network>().extend();
store<xag_network>().current() = xag;
Expand All @@ -166,7 +158,7 @@ namespace alice
img_network img = store<img_network>().current();

auto fcost1 = total_fc_cost( img );
print_stats( img );
also::print_stats( img );

cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 3u;
Expand All @@ -180,7 +172,7 @@ namespace alice
img = cleanup_dangling( img );

auto fcost2 = total_fc_cost( img );
print_stats( img );
also::print_stats( img );
std::cout << "fcost: " << fcost1 << " to " << fcost2 << std::endl;

store<img_network>().extend();
Expand All @@ -189,7 +181,7 @@ namespace alice
else if( is_set( "img_all" ) )
{
img_network img = store<img_network>().current();
print_stats( img );
also::print_stats( img );

cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 3u;
Expand All @@ -198,7 +190,7 @@ namespace alice
cut_rewriting( img, resyn, ps );
img = cleanup_dangling( img );

print_stats( img );
also::print_stats( img );

store<img_network>().extend();
store<img_network>().current() = img;
Expand All @@ -207,18 +199,18 @@ namespace alice
{
xmg_network xmg = store<xmg_network>().current();

print_stats( xmg );
also::print_stats( xmg );

xmg_npn_resynthesis resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
cut_rewriting( xmg, resyn, ps );
xmg = cleanup_dangling( xmg );

print_stats( xmg );
also::print_stats( xmg );

store<xmg_network>().extend();
store<xmg_network>().current() = xmg;
store<xmg_network>().current() = cleanup_dangling( xmg );
}
}

Expand Down
15 changes: 15 additions & 0 deletions src/commands/lut_mapping.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ namespace alice
add_option( "cut_size, -k", cut_size, "set the cut size from 2 to 8, default = 4" );
add_flag( "--verbose, -v", "print the information" );
add_flag( "--satlut, -s", "satlut mapping" );
add_flag( "--aig, -a", "LUT mapping for AIG" );
add_flag( "--xmg, -x", "LUT mapping for XMG" );
add_flag( "--mig, -m", "LUT mapping for MIG" );
add_flag( "--opt_img, -o", "Using optimal IMG size for 3-input function as the cost function" );
Expand Down Expand Up @@ -57,6 +58,20 @@ namespace alice
store<klut_network>().extend();
store<klut_network>().current() = klut;
}
else if( is_set( "aig" ) )
{
assert( store<aig_network>().size() > 0 );
aig_network aig = store<aig_network>().current();

mapping_view<aig_network, true> mapped_aig{aig};
ps.cut_enumeration_ps.cut_size = cut_size;
lut_mapping<mapping_view<aig_network, true>, true>( mapped_aig, ps );

/* collapse into k-LUT network */
const auto klut = *collapse_mapped_network<klut_network>( mapped_aig );
store<klut_network>().extend();
store<klut_network>().current() = klut;
}
else if( is_set( "mig" ) )
{
/* derive some MIG */
Expand Down
77 changes: 14 additions & 63 deletions src/commands/lut_resyn.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -70,46 +70,25 @@ namespace alice
if( is_set( "xmg" ) )
{
xmg_network xmg;
xmg_npn_resynthesis resyn;
xmg = node_resynthesis<xmg_network>( klut, resyn );

/* add to store */
if( is_set( "new_entry" ) )
{
store<xmg_network>().extend();
store<xmg_network>().current() = xmg;
}

if( is_set( "enable_direct_mapping" ) )
{
/* make the xmg from aig one-to-one mapping as the
* basiline xmg*/
depth_view xmg_depth1{xmg};
assert( store<aig_network>().size() > 0 );
aig_network aig = store<aig_network>().current();
auto xmg_baseline = also::xmg_from_aig( aig );

depth_view xmg_depth2{xmg_baseline};

std::cout << "depth 1: " << xmg_depth1.depth()
<< "depth 2: " << xmg_depth2.depth()
<< std::endl;

/*select the XMG that has fewer number of nodes
* naive method currently
* */
if( xmg_depth2.depth() < xmg_depth1.depth() )
{
xmg = also::xmg_from_aig( aig );
/* add to store */
if( is_set( "new_entry" ) )
{
store<xmg_network>().extend();
store<xmg_network>().current() = xmg;
}
}
xmg = also::xmg_from_aig( aig );
}
else
{
xmg_npn_resynthesis resyn;
xmg = node_resynthesis<xmg_network>( klut, resyn );
}

/* add to store */
if( is_set( "new_entry" ) )
{
store<xmg_network>().extend();
store<xmg_network>().current() = cleanup_dangling( xmg );
}

}
else if( is_set( "xmg3" ) )
{
Expand All @@ -123,10 +102,6 @@ namespace alice
store<xmg_network>().extend();
store<xmg_network>().current() = xmg;
}

depth_view xmg_depth{xmg};
std::cout << "[I/O:" << xmg.num_pis() << "/" << xmg.num_pos() << "] XMG3 gates: "
<< xmg.num_gates() << " XMG3 depth: " << xmg_depth.depth() << std::endl;
}
else if( is_set( "m5ig" ) )
{
Expand All @@ -136,11 +111,7 @@ namespace alice
{
m5ig_npn_resynthesis resyn;
node_resynthesis( m5ig, klut, resyn );
//m5ig = node_resynthesis<m5ig_network>( klut, resyn );

depth_view m5ig_depth{m5ig};
std::cout << "[I/O:" << m5ig.num_pis() << "/" << m5ig.num_pos() << "] M5IG gates: "
<< m5ig.num_gates() << " M5IG depth: " << m5ig_depth.depth() << std::endl;
m5ig = node_resynthesis<m5ig_network>( klut, resyn );
}
else
{
Expand All @@ -167,10 +138,6 @@ namespace alice
store<img_network>().extend();
store<img_network>().current() = img;
}

depth_view img_depth{img};
std::cout << "[I/O:" << img.num_pis() << "/" << img.num_pos() << "] IMG gates: "
<< img.num_gates() << " IMG depth: " << img_depth.depth() << std::endl;
}
else if( is_set( "test_m3ig" ) )
{
Expand All @@ -194,10 +161,6 @@ namespace alice
resyn( mig, maj, pis.begin(), pis.end(), [&]( auto const& f ) {
mig.create_po( f );
} );

depth_view mig_depth{mig};
std::cout << "[I/O:" << mig.num_pis() << "/" << mig.num_pos() << "] MIG gates: "
<< mig.num_gates() << " MIG depth: " << mig_depth.depth() << std::endl;
}
else if( is_set( "test_m5ig" ) )
{
Expand All @@ -223,10 +186,6 @@ namespace alice
resyn( m5ig, maj, pis.begin(), pis.end(), [&]( auto const& f ) {
m5ig.create_po( f );
} );

depth_view m5ig_depth{m5ig};
std::cout << "[I/O:" << m5ig.num_pis() << "/" << m5ig.num_pos() << "] M5IG gates: "
<< m5ig.num_gates() << " M5IG depth: " << m5ig_depth.depth() << std::endl;
}
else if( is_set( "xag" ) )
{
Expand All @@ -253,10 +212,6 @@ namespace alice
store<xag_network>().extend();
store<xag_network>().current() = xag;
}

depth_view xag_depth{xag};
std::cout << "[I/O:" << xag.num_pis() << "/" << xag.num_pos() << "] xag gates: "
<< xag.num_gates() << " xag depth: " << xag_depth.depth() << std::endl;
}
else
{
Expand All @@ -269,10 +224,6 @@ namespace alice
store<mig_network>().extend();
store<mig_network>().current() = mig;
}

depth_view mig_depth{mig};
std::cout << "[I/O:" << mig.num_pis() << "/" << mig.num_pos() << "] MIG gates: "
<< mig.num_gates() << " MIG depth: " << mig_depth.depth() << std::endl;
}
}

Expand Down

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