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  • Getting Started with Vim

    Updated Sep 17, 2024
  • sus-compiler Public

    Forked from pc2/sus-compiler

    A new Hardware Design Language that keeps you in the driver's seat

    Rust GNU General Public License v3.0 Updated Aug 7, 2024
  • 5G RRU reference design - 8T8R using 2 ADI ADRV9026s, FPGA XZCU15EG

    Verilog 1 Updated May 27, 2024
  • Rosebud Public

    Forked from ucsdsysnet/Rosebud

    Framework for FPGA-accelerated Middlebox Development

    Verilog MIT License Updated May 17, 2024
  • learn-riscv Public

    Forked from riscv/learn

    Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

    Updated Apr 25, 2024
  • Slaclab PCIe implementation

    VHDL Other Updated Mar 30, 2024
  • Rocket Chip Generator

    Scala Other Updated Feb 19, 2024
  • FEC Public

    Forked from dshekhalev/FEC

    FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

    SystemVerilog MIT License Updated Jan 17, 2024
  • Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

    Tcl Updated Jan 17, 2024
  • AutoSA Public

    Forked from UCLA-VAST/AutoSA

    AutoSA: Polyhedral-Based Systolic Array Compiler

    C++ MIT License Updated Dec 26, 2023
  • TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators.

    C MIT License Updated Nov 24, 2023
  • chipyard Public

    Forked from ucb-bar/chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    C BSD 3-Clause "New" or "Revised" License Updated Nov 15, 2023
  • firesim Public

    Forked from firesim/firesim

    FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

    Scala Other Updated Nov 15, 2023
  • litex Public

    Forked from enjoy-digital/litex

    Build your hardware, easily!

    C Other Updated Nov 15, 2023
  • JavaScript MIT License Updated Nov 8, 2023
  • sv-axis Public

    AXI4-Stream basic building blocks in SystemVerilog

    SystemVerilog MIT License Updated Nov 6, 2023
  • ruckus Public

    Forked from slaclab/ruckus

    Vivado build system

    Tcl Other Updated Nov 4, 2023
  • surf Public

    Forked from slaclab/surf

    A huge VHDL library for FPGA development

    VHDL Other Updated Nov 3, 2023
  • A Chisel RTL generator for network-on-chip interconnects

    Scala BSD 3-Clause "New" or "Revised" License Updated Oct 24, 2023
  • sv-practice Public

    Labs to pratice digital design with System Verilog

    SystemVerilog 1 Updated Oct 17, 2023
  • kvm-pcie Public

    Installing KVM and passthrough PCIe (Xilinx FPGA AU200)

    Shell 1 MIT License Updated Oct 3, 2023
  • matlab-5GNR Public

    Matlab implementations of several 5G L1 functions

    MATLAB 2 MIT License Updated Oct 2, 2023
  • wol-courses Public

    SCSS Updated Sep 27, 2023
  • Bluespec Compiler (BSC)

    Haskell Other Updated Sep 21, 2023
  • sv-common Public

    SystemVerilog Packages for RTL design and verification

    SystemVerilog MIT License Updated Sep 14, 2023
  • Implementation of a 16-bit pipeline CPU

    VHDL Updated Jun 14, 2023
  • cocotb Public

    Studying cocotb

    VHDL Updated Jun 7, 2023
  • Guide to get familiar with DFX flow

    Tcl Updated May 5, 2023
  • fpga-orchard Public

    Forked from zcash/orchard

    TBD

    Rust Other Updated Feb 28, 2023
  • website_tmpl Public template

    Forked from alshedivat/al-folio

    A beautiful, simple, clean, and responsive Jekyll theme for academics

    JavaScript MIT License Updated Sep 21, 2022