Creation Date - October 17th, 2020
This Single Stage RISC Processor was loosely based on ARM/MIPS instruction set and simulated in VHDL. Its components include the Instruction Memory, Control unit, Registers, ALU, and Data Memory. The instructions are 16 bits in length.
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| Date | Log |
|---|---|
| 2020/10/27 | Trevor Broady, Nikita Popel - Outlined Instruction Set |
| 2020/11/03 | Trevor Broady, Nikita Popel - Tested Individual units, completed the datapath, and tested the composite datapath |
| 2020/11/10 | Trevor Broady, Nikita Popel - Designed and built the control unit. Intgegrated control unit with datapath |
| 2020/11/17 | Trevor Broady, Nikita Popel - Made sure final design was working |