cores/e1: Fix CRC error marker in BD out fifo

bd_done isn't aligned with df_valid so can't use the latter as the clock enable Signed-off-by: Sylvain Munaut <[email protected]>
no2fpga · May 20, 2020 · 51b60b6 · 51b60b6
1 parent 883ecfa
commit 51b60b6
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/rtl/e1_rx.v b/rtl/e1_rx.v
@@ -192,10 +192,10 @@ module e1_rx #(
 	always @(posedge clk or posedge rst)
 		if (rst)
 			bd_crc_e <= 2'b00;
-		else if (df_valid)
+		else
 			bd_crc_e <= (bd_done) ? 2'b00 : (bd_crc_e | {
-				df_err_crc &  df_frame[3],	// CRC error in second SMF
-				df_err_crc & ~df_frame[3]	// CRC error in first SMF
+				df_valid & df_err_crc &  df_frame[3],	// CRC error in second SMF
+				df_valid & df_err_crc & ~df_frame[3]	// CRC error in first SMF
 			});
 
 	// Buffer write