icacheMissQueue: support different client visit

debug/Makefile

@@ -13,11 +13,12 @@ EMU_ARGS = B=$(B) E=$(E) V=$(V)
 # ------------------------------------------------------------------
 
 cache:
-	$(MAKE) -C $(AM_HOME)/tests/cachetest $(ARCH) ALL=loader $(EMU_ARGS) run 2>&1 | tee > loader.log
+	$(MAKE) -C $(AM_HOME)/tests/cachetest $(ARCH) ALL=loader $(EMU_ARGS) run 
+	#2>&1 | tee > loader.log
 	#2>&1 | tee > loader.log
 
 cpu:
-	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) ALL=hello-str $(EMU_ARGS) run 2>&1 | tee > hello-str.log
+	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) ALL=dummy $(EMU_ARGS) run 2>&1 | tee > dummy.log
 
 # ------------------------------------------------------------------
 # run different test sets

src/main/scala/xiangshan/cache/icache.scala

@@ -42,7 +42,7 @@ trait HasICacheParameters extends HasL1CacheParameters {
   def RVCInsLen = 16
 
   // icache Queue
-  def nMSHRs = 4
+  def nMSHRs = 2
   val groupAlign = log2Up(FetchWidth * 4 * 2)
   def groupPC(pc: UInt): UInt = Cat(pc(PAddrBits-1, groupAlign), 0.U(groupAlign.W))
 
@@ -275,21 +275,22 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
   //ICache MissQueue
   val icacheMissQueue = Module(new IcacheMissQueue(edge))
   val blocking = RegInit(false.B)
+  val isICacheResp = icacheMissQueue.io.resp.valid && icacheMissQueue.io.resp.bits.clientID === cacheID.U(2.W)
   icacheMissQueue.io.req.valid := s3_miss && (io.flush === 0.U) && !blocking//TODO: specificate flush condition
-  icacheMissQueue.io.req.bits.apply(missAddr=s3_tlb_resp.paddr,missWaymask=s3_wayMask)
+  icacheMissQueue.io.req.bits.apply(missAddr=s3_tlb_resp.paddr,missWaymask=s3_wayMask,source=cacheID.U(2.W))
   icacheMissQueue.io.resp.ready := io.resp.ready
   icacheMissQueue.io.flush := io.flush(1)
 
   when(icacheMissQueue.io.req.fire()){blocking := true.B}
-  .elsewhen(icacheMissQueue.io.resp.fire()){blocking := false.B}
+  .elsewhen(icacheMissQueue.io.resp.fire() && isICacheResp){blocking := false.B}
 
   //cache flush register
   val icacheFlush = WireInit(false.B)
   val cacheflushed = RegInit(false.B)
   BoringUtils.addSink(icacheFlush, "FenceI")
   XSDebug("[Fence.i] icacheFlush:%d, cacheflushed:%d\n",icacheFlush,cacheflushed)
-  when(icacheFlush && blocking && !icacheMissQueue.io.resp.valid){ cacheflushed := true.B}
-  .elsewhen(icacheMissQueue.io.resp.valid && cacheflushed) {cacheflushed := false.B }
+  when(icacheFlush && blocking && !isICacheResp){ cacheflushed := true.B}
+  .elsewhen(isICacheResp && cacheflushed) {cacheflushed := false.B }
 
   //TODO: Prefetcher
 
@@ -325,7 +326,7 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
   //icache flush: only flush valid Array register
   when(icacheFlush){ validArray := 0.U }
 
-  val refillDataVec = icacheMissQueue.io.resp.bits.asTypeOf(Vec(blockWords,UInt(wordBits.W)))
+  val refillDataVec = icacheMissQueue.io.resp.bits.data.asTypeOf(Vec(blockWords,UInt(wordBits.W)))
   val refillDataOut = cutHelper(refillDataVec, s3_req_pc(5,1),s3_req_mask )
 
   s3_ready := ((io.resp.fire() || !s3_valid) && !blocking) || (blocking && icacheMissQueue.io.resp.valid)

src/main/scala/xiangshan/cache/icacheMissQueue.scala

@@ -51,23 +51,25 @@ class IcacheMissReq extends ICacheBundle
 {
     val addr  = UInt(PAddrBits.W)
     val waymask = UInt(PredictWidth.W)
-    //val clientID = Bool()
-    def apply(missAddr:UInt, missWaymask:UInt) = {
+    val clientID = UInt(2.W)
+    def apply(missAddr:UInt, missWaymask:UInt, source:UInt) = {
       this.addr := missAddr
       this.waymask := missWaymask
+      this.clientID := source
     }
 }
 
 class IcacheMissResp extends ICacheBundle
 {
     val data = UInt(blockBits.W)
+    val clientID = UInt(2.W)
 }
 
 class IcacheMissEntry(edge: TLEdgeOut) extends ICacheMissQueueModule
 {
     val io = IO(new Bundle{
         // MSHR ID
-        val id = Input(UInt())
+        val id = Input(UInt(log2Up(nMSHRs).W))
 
         val req = Flipped(DecoupledIO(new IcacheMissReq))
         val resp = DecoupledIO(new IcacheMissResp)
@@ -149,6 +151,7 @@ class IcacheMissEntry(edge: TLEdgeOut) extends ICacheMissQueueModule
 
       is(s_wait_resp){
         io.resp.bits.data := refillDataReg.asUInt
+	io.resp.bits.clientID := req.clientID
         when(io.resp.fire() || needFlush ){ state := s_idle }
       }
 
@@ -243,4 +246,4 @@ class IcacheMissQueue(edge: TLEdgeOut) extends ICacheMissQueueModule
   io.refill     <> refill_arb.io.out
 
   TLArbiter.lowestFromSeq(edge, io.mem_acquire, entries.map(_.io.mem_acquire))
-}
+}