forked from kindsoldier/stm32-f1-freertos-opencm3
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathi2creg.c
241 lines (175 loc) · 7.66 KB
/
i2creg.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
/* Author, Copyright: Oleg Borodin <[email protected]> 2018 */
#include <libopencm3/stm32/i2c.h>
#include <stdlib.h>
#include <i2creg.h>
#include <FreeRTOS.h>
#include <task.h>
uint16_t i2c_read_seq(uint32_t i2c, uint16_t addr, uint8_t reg, uint8_t *data, uint16_t len) {
taskENTER_CRITICAL();
while ((I2C_SR2(i2c) & (I2C_SR2_BUSY)));
i2c_enable_ack(i2c);
i2c_send_start(i2c);
/* I2C_EVENT_MASTER_MODE_SELECT EV5: BUSY, MSL and SB */
while (!((I2C_SR1(i2c) & I2C_SR1_SB) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY))));
i2c_send_7bit_address(i2c, addr, I2C_WRITE);
/* I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED EV6: BUSY, MSL, ADDR, TXE and TRA */
while (!( (I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_ADDR)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA)) ));
(void)I2C_SR2(i2c);
i2c_send_data(i2c, reg);
/* I2C_EVENT_MASTER_BYTE_TRANSMITTED EV8_2: TRA, BUSY, MSL, TXE and BTF */
while (!((I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_BTF)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA))));
i2c_send_start(i2c);
/* I2C_EVENT_MASTER_MODE_SELECT EV5: BUSY, MSL and SB */
while (!((I2C_SR1(i2c) & I2C_SR1_SB) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY))));
i2c_send_7bit_address(i2c, addr, I2C_READ);
/* I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED EV6: BUSY, MSL and ADDR */
while (!( (I2C_SR1(i2c) & (I2C_SR1_ADDR)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)) ));
uint16_t i;
for (i = 0; i < len; i++) {
if (i == len - 1) {
i2c_disable_ack(i2c);
//i2c_nack_current(i2c);
i2c_send_stop(i2c);
}
/* I2C_EVENT_MASTER_BYTE_RECEIVED EV7: BUSY, MSL and RXNE */
while (!(I2C_SR1(i2c) & I2C_SR1_RxNE));
data[i] = i2c_get_data(i2c);
}
while ((I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)));
taskEXIT_CRITICAL();
return ++i;
}
uint16_t i2c_write_seq(uint32_t i2c, uint16_t addr, uint8_t reg, uint8_t *data, uint16_t len) {
while ((I2C_SR2(i2c) & (I2C_SR2_BUSY)));
i2c_enable_ack(i2c);
i2c_send_start(i2c);
/* I2C_EVENT_MASTER_MODE_SELECT EV5: BUSY, MSL and SB */
while (!((I2C_SR1(i2c) & I2C_SR1_SB) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY))));
i2c_send_7bit_address(i2c, addr, I2C_WRITE);
/* I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED EV6: BUSY, MSL, ADDR, TXE and TRA */
while (!( (I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_ADDR)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA)) ));
//(void)I2C_SR2(i2c);
i2c_send_data(i2c, reg);
/* I2C_EVENT_MASTER_BYTE_TRANSMITTED EV8_2: TRA, BUSY, MSL, TXE and BTF */
while (!((I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_BTF)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA))));
uint16_t i;
for (i = 0; i < len; i++) {
i2c_send_data(i2c, data[i]);
/* I2C_EVENT_MASTER_BYTE_TRANSMITTED EV8_2: TRA, BUSY, MSL, TXE and BTF */
while (!((I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_BTF)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA))));
}
i2c_send_stop(i2c);
while ((I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)));
return ++i;
}
void i2c_write_reg(uint32_t i2c, uint16_t addr, uint8_t reg, uint8_t data) {
i2c_write_seq(i2c, addr, reg, &data, 1);
}
uint8_t i2c_read_reg(uint32_t i2c, uint16_t addr, uint8_t reg) {
uint8_t data;
i2c_read_seq(i2c, addr, reg, &data, 1);
return data;
}
void i2c_set_bit_field(uint32_t i2c, uint16_t addr, uint8_t reg, uint8_t base, uint8_t len, uint8_t data) {
uint8_t rdata = 0;
rdata = i2c_read_reg(i2c, addr, reg);
uint8_t mask = 0xFF & ((0xFF << (base + len)) | 0xFF >> (8 - base));
rdata &= mask;
data <<= base;
data &= ~mask;
rdata |= data;
i2c_write_reg(i2c, addr, reg, rdata);
}
void i2c_clean_bit_field(uint32_t i2c, uint16_t addr, uint8_t reg, uint8_t base, uint8_t len) {
uint8_t rdata = 0;
rdata = i2c_read_reg(i2c, addr, reg);
uint8_t mask = 0xFF & ((0xFF << (base + len)) | 0xFF >> (8 - base));
rdata &= mask;
i2c_write_reg(i2c, addr, reg, rdata);
}
void i2c_set_one_bit(uint32_t i2c, uint16_t addr, uint8_t reg, uint8_t base) {
uint8_t rdata = i2c_read_reg(i2c, addr, reg);
rdata |= (1 << base);
i2c_write_reg(i2c, addr, reg, rdata);
}
void i2c_clean_one_bit(uint32_t i2c, uint16_t addr, uint8_t reg, uint8_t base) {
uint8_t rdata = i2c_read_reg(i2c, addr, reg);
rdata &= ~(1 << base);
i2c_write_reg(i2c, addr, reg, rdata);
}
void i2c_set_bit(uint32_t i2c, uint16_t addr, uint8_t reg, uint8_t mask) {
uint8_t rdata = i2c_read_reg(i2c, addr, reg);
rdata |= mask;
i2c_write_reg(i2c, addr, reg, rdata);
}
void i2c_clean_bit(uint32_t i2c, uint16_t addr, uint8_t reg, uint8_t mask) {
uint8_t rdata = i2c_read_reg(i2c, addr, reg);
rdata &= ~(mask);
i2c_write_reg(i2c, addr, reg, rdata);
}
#if 0
void _i2c_write_reg(uint32_t i2c, uint16_t addr, uint8_t reg, uint8_t data) {
i2c_enable_ack(i2c);
i2c_send_start(i2c);
/* I2C_EVENT_MASTER_MODE_SELECT EV5: BUSY, MSL and SB */
while (!((I2C_SR1(i2c) & I2C_SR1_SB) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY))));
i2c_send_7bit_address(i2c, addr, I2C_WRITE);
/* I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED EV6: BUSY, MSL, ADDR, TXE and TRA */
while (!( (I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_ADDR)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA)) ));
//(void)I2C_SR2(i2c);
i2c_send_data(i2c, reg);
/* I2C_EVENT_MASTER_BYTE_TRANSMITTED EV8_2: TRA, BUSY, MSL, TXE and BTF */
while (!((I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_BTF)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA))));
i2c_send_data(i2c, data);
/* I2C_EVENT_MASTER_BYTE_TRANSMITTED EV8_2: TRA, BUSY, MSL, TXE and BTF */
while (!((I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_BTF)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA))));
i2c_send_stop(i2c);
while ((I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)));
}
uint8_t _i2c_read_reg(uint32_t i2c, uint16_t addr, uint8_t reg) {
uint8_t data = 0;
i2c_enable_ack(i2c);
i2c_send_start(i2c);
/* I2C_EVENT_MASTER_MODE_SELECT EV5: BUSY, MSL and SB */
while (!((I2C_SR1(i2c) & I2C_SR1_SB) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY))));
i2c_send_7bit_address(i2c, addr, I2C_WRITE);
/* I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED EV6: BUSY, MSL, ADDR, TXE and TRA */
while (!( (I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_ADDR)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA)) ));
(void)I2C_SR2(i2c);
i2c_send_data(i2c, reg);
/* I2C_EVENT_MASTER_BYTE_TRANSMITTED EV8_2: TRA, BUSY, MSL, TXE and BTF */
while (!((I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_BTF)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA))));
i2c_send_start(i2c);
/* I2C_EVENT_MASTER_MODE_SELECT EV5: BUSY, MSL and SB */
while (!((I2C_SR1(i2c) & I2C_SR1_SB) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY))));
i2c_send_7bit_address(i2c, addr, I2C_READ);
/* I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED EV6: BUSY, MSL and ADDR */
while (!( (I2C_SR1(i2c) & (I2C_SR1_ADDR)) &
(I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)) ));
i2c_disable_ack(i2c);
i2c_send_stop(i2c);
/* I2C_EVENT_MASTER_BYTE_RECEIVED EV7: BUSY, MSL and RXNE */
while (!( (I2C_SR1(i2c) & I2C_SR1_RxNE )));
data = i2c_get_data(i2c);
while ((I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)));
return data;
}
#endif
/* EOF */