simple_projects

Examples of simple modules in Verilog.

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
Task 1.7.v		Task 1.7.v
task 1.8.v		task 1.8.v
task 1.1-tb.v		task 1.1-tb.v
task 1.1.png		task 1.1.png
task 1.1.v		task 1.1.v
task 1.10-tb.v		task 1.10-tb.v
task 1.10.png		task 1.10.png
task 1.10.v		task 1.10.v
task 1.11-tb.v		task 1.11-tb.v
task 1.11.png		task 1.11.png
task 1.11.v		task 1.11.v
task 1.12-tb.v		task 1.12-tb.v
task 1.12.png		task 1.12.png
task 1.12.v		task 1.12.v
task 1.13-tb.v		task 1.13-tb.v
task 1.13.png		task 1.13.png
task 1.13.v		task 1.13.v
task 1.14-tb.v		task 1.14-tb.v
task 1.14.png		task 1.14.png
task 1.14.v		task 1.14.v
task 1.2-tb.v		task 1.2-tb.v
task 1.2.png		task 1.2.png
task 1.2.v		task 1.2.v
task 1.3-tb.v		task 1.3-tb.v
task 1.3.png		task 1.3.png
task 1.3.v		task 1.3.v
task 1.4-tb.v		task 1.4-tb.v
task 1.4.png		task 1.4.png
task 1.4.v		task 1.4.v
task 1.5-tb.v		task 1.5-tb.v
task 1.5.png		task 1.5.png
task 1.5.v		task 1.5.v
task 1.6-tb.v		task 1.6-tb.v
task 1.6.png		task 1.6.png
task 1.6.v		task 1.6.v
task 1.7-tb.v		task 1.7-tb.v
task 1.7.png		task 1.7.png
task 1.8-tb.v		task 1.8-tb.v
task 1.8.png		task 1.8.png
task 1.9-tb.v		task 1.9-tb.v
task 1.9.png		task 1.9.png
task 1.9.v		task 1.9.v

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