13 Pull requests merged by 8 people

• [Skip CI] Extending RESOURCES.md document

  #2629 merged Jan 10, 2025

• Fully support the Write-Back mode of the HPDcache in the CVA6

  #2691 merged Jan 10, 2025

• wt_axi_adapter: Fix addr width parametrisation

  #2697 merged Jan 10, 2025

• wt_dcache_buffer: Avoid out-of-range user signal access

  #2698 merged Jan 9, 2025

• doc: RVZicntr extension can be not supported

  #2699 merged Jan 9, 2025

• Make PMP disableable

  #2692 merged Jan 9, 2025

• 🐛 Fix icache AXI read len

  #2696 merged Jan 8, 2025

• Code coverage : Add option to support coverage condition with arithmetic operations

  #2694 merged Jan 8, 2025

• csr_regfile: Fix irq/ex delegation in RVH

  #2689 merged Jan 8, 2025

• update readme with information how to generate bitstream for agilex 7

  #2690 merged Jan 8, 2025

• Fix partially #1181

  #2686 merged Jan 8, 2025

• Altera flow support

  #2649 merged Jan 7, 2025

• Fix #2665 #2400 #2657

  #2685 merged Jan 7, 2025

12 Issues closed by 6 people

• [BUG] <title> riscv-test with virtual memory enabled fails on target cv64a6_imafdc_sv39_hpdcache in write-back mode

  #2603 closed Jan 10, 2025

• MIP CSR is failing while verifying access mode

  #1161 closed Jan 9, 2025

• [BUG] replace FORMAL directive by VERILATOR

  #1181 closed Jan 9, 2025

• Condition coverage limitation

  #1902 closed Jan 8, 2025

• [BUG] Result of riscv_unaligned_load_store_test is inconsistent

  #2645 closed Jan 8, 2025

• [BUG] RVFI agent & tandem mode simulation performance degradation

  #2556 closed Jan 8, 2025

• [BUG] Instruction Access Fault during transition from Machine to Hypervisor/Supervisor Mode

  #2687 closed Jan 7, 2025

• [BUG] PMP CSR : NAPOT MODE isn't supported

  #2400 closed Jan 7, 2025

• [BUG] PMPCFG : Dead code in pmp module

  #2665 closed Jan 7, 2025

• Reproducing Dhrystone performance numbers

  #1035 closed Jan 6, 2025

• [BUG] bootrom_32.sv is not aligned with the cv32a6.dts

  #1485 closed Jan 6, 2025

• Dual issue

  #1385 closed Jan 6, 2025

4 Issues opened by 2 people

• OpenPiton configuration of CVA6 cannot boot Linux on UltraScale+ FPGA

  #2700 opened Jan 10, 2025

• [BUG] SBE/UBE/MBE Bit in `mstatus` Register Does Not Affect Endianness of Explicit Memory Accesses

  #2695 opened Jan 8, 2025

• [BUG] interrupts delegattion Not Masked in M-Mode as Expected

  #2693 opened Jan 8, 2025

• [BUG] Incorrect `stval` value after illegal instruction exception while `mstatus.TVM` flag is activated in HS-mode

  #2688 opened Jan 7, 2025

25 Unresolved conversations

Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.

• Adding support for ZCMT Extension for Code-Size Reduction in CVA6

  #2659 commented on Jan 9, 2025 • 10 new comments

• [RVV] CVA6 re-parametrization and MMU interface

  #2652 commented on Jan 12, 2025 • 2 new comments

• Update rvfi_tracer and cva6.py

  #2684 commented on Jan 6, 2025 • 0 new comments

• PMP Verif Plan and tests

  #2648 commented on Jan 6, 2025 • 0 new comments

• Add Support for Digilent Arty-A7 100T FPGA Board

  #2581 commented on Jan 7, 2025 • 0 new comments

• PR for adding Questa support for CVA6

  #2532 commented on Jan 10, 2025 • 0 new comments

• How to bring printf support in simulation environment ?

  #2426 commented on Jan 11, 2025 • 0 new comments

• Issue with MTVEC CSR default value

  #1312 commented on Jan 9, 2025 • 0 new comments

• CVA6-specific behaviour for WLRL CSR fields

  #1053 commented on Jan 9, 2025 • 0 new comments

• PMP CSRs access mode failures

  #1178 commented on Jan 9, 2025 • 0 new comments

• [Spike] : Mismatch of address mapping between spike & RTL

  #1625 commented on Jan 9, 2025 • 0 new comments

• [BUG] SPIKE model is not configurable with TvalEn core option

  #2243 commented on Jan 9, 2025 • 0 new comments

• [BUG] remove ifndef VERILATOR directives

  #1180 commented on Jan 9, 2025 • 0 new comments

• cebreak tests are failing in latest cva6 riscv-arch-test suite

  #1413 commented on Jan 9, 2025 • 0 new comments

• [BUG] spike : Update CVXIF instruction

  #2626 commented on Jan 9, 2025 • 0 new comments

• Immediate assertions in the CVA6 RTL

  #1624 commented on Jan 8, 2025 • 0 new comments

• [BUG] PMPCFG WARL behavior

  #2024 commented on Jan 7, 2025 • 0 new comments

• [BUG] [CV32A65X] Writes into PMPADDR registers do not follow specification

  #2657 commented on Jan 7, 2025 • 0 new comments

• [BUG] `minstret` and `mcycle` do not increment in debug mode, while `dcsr.stopcount` is set to 0 (normal mode)

  #2297 commented on Jan 7, 2025 • 0 new comments

• [BUG] Allowing illegal access to addresses outside the PMP range and memory boundaries.

  #2055 commented on Jan 7, 2025 • 0 new comments

• Spyglass Warnings increased by new PMP entries

  #2365 commented on Jan 7, 2025 • 0 new comments

• [BUG] Delay in enforcing PMP rules leading to attacker can read 128bits of data in PMP region

  #2567 commented on Jan 7, 2025 • 0 new comments

• Reading mcycle CSR via setStats() makes simulation fail

  #1421 commented on Jan 6, 2025 • 0 new comments

• [TASK] Parametrization

  #1451 commented on Jan 6, 2025 • 0 new comments

• scoreboard.sv [BUG] : RTL assertion failed

  #2376 commented on Jan 6, 2025 • 0 new comments