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KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

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You'll own nothing and be happy!

I am a professional embedded systems engineer. I started in 2021 with logic design, motivated to learn. My goal was to implement a RISC-V Linux SoC because I love Linux. Now, that goal has come true. In the future, I aim to work on advanced designs and improvements, step by step.

RISC-V ASIC/FPGA uLinux/MMU Linux/XV6 SoCs:

If you're interested in trying out the KianV SV32 (MMU) RV32IMA Zicntr SSTC Linux/XV6 SoC, complete with virtual memory support, check out the link here: KianV SV32 RV32IMA Zicntr.

Checkout my KianV RISC-V uLinux SoC! FPGA implementation details here. I have made a uLinux ASIC with TinyTapeout. Check my designs here.

Kianv uLinux ASIC Soc TT05

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|  |/  |__|.---.-.-----.|   |   |     |_|__|.-----.--.--.--.--.
|     <|  ||  _  |     ||   |   |       |  ||     |  |  |_   _|
|__|\__|__||___._|__|__| \_____/|_______|__||__|__|_____|__.__|

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KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

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  • C 34.8%
  • Assembly 29.2%
  • Verilog 23.8%
  • Tcl 5.3%
  • SystemVerilog 4.1%
  • Makefile 1.0%
  • Other 1.8%