A dynamic partial reconfiguraton tutorial for ZYBO and MPSoC ZU106 using PCAP.
Part of my thesis research
In this tutorial, I developed a simple module that performs addition and subtraction on two memory maped axi-lite signal and return the result in the same interface.
The steps may not be optimal and some elements could be excluded.
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Create a block design
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Add the Axi-Lite communication module | Status
- The decupler and the gpio are not used
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Make external the ports of the AXI
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Create a top module that include the block design and the reconfigurable part.
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Open Syntesised Design and floorplan the reconfigurable design and area. Save it the .xdc file.
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In the vivado tools click on Enable Dynamic Function eXchange
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Hover above the sources, select the reconfigurable module, right click on Create Partition Definition with the name you like
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In the vivado tools click on Dynamic Function eXchange Wizard
- Add your module to the partition | model it by view the existing one in the edit. (For logic design, only the file is needed).
- Click on next, to the Edit Configurations tab.
- Add the different configurations and select the different logic to each of the configurations.
- Click on next, to the Edit Configurations Runs tab.
- Select the automatic configuration.
- Finish from the Wizard
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Generate the Bitstream.
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In the design runs, there is a report, and on the vivado runs folder, there are the full bitstream and the partial ones, labeled impl1 and the name gives respectively.
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Export the hardware and get to vitis.
- In the .spr and the cpu tab modify the bsp settings to add the nessesary libraries to the Board Support Package.
- Zybo : xilffs
- MPSoC : xilffs,xilfpga, xilsecure
- In the application lscript.ld adjust the heap size to be able to store the partial bitstream.
- Youtube video that explains someof this stuff. He is a bad person, putting the code behind a pay wall but at least he helped understand some of the basics.
- Youtube video and GitHub. He has different repos but that helped me the most.