A FPGA friendly 32 bit RISC-V CPU implementation

Various HDL (Verilog) IP Cores

A Linux-capable RISC-V multicore for and by the world

BaseJump STL: A Standard Template Library for SystemVerilog

RISC-V SoC on the iCE40UP5K.

There are many RISC V projects on iCE40. This one is mine.

Sega Saturn for MiSTer

Universal utility for programming FPGA

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Multiple test designs for the iCE40UP5K-B-EVN board.

80186 compatible SystemVerilog CPU core and FPGA reference design

Python Wrapper for GLI

PicoRV32 - A Size-Optimized RISC-V CPU

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

A minimal GPU design in Verilog to learn how GPUs work from the ground up

An open source GPU based off of the AMD Southern Islands ISA.

A CPU tool for benchmarking the peak of floating points

An application framework for rapid prototyping of 3D applications

Sample benchmark demonstrating the VK_KHR_cooperative_matrix extension

A javascript implementation of the Separating Axis Theorem for convex polygons and polyhedra

RapidXML fork; XML namespacing, per-element parsing, etc

roadnetworkgenerator

computational geometry algorithms

Hull, Delaunay and Voronoi algorithms in Unity

Yet Another Rogue-Like

a simple voxel engine for Unity