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OpenROAD-flow-scripts Public
Forked from The-OpenROAD-Project/OpenROAD-flow-scriptsOpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Verilog Other UpdatedJun 10, 2023 -
cva6 Public
Forked from openhwgroup/cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
SystemVerilog Other UpdatedJun 6, 2023 -
e203_hbirdv2 Public
Forked from riscv-mcu/e203_hbirdv2The Ultra-Low Power RISC-V Core
Verilog Apache License 2.0 UpdatedMar 27, 2023 -
verilator Public
Forked from verilator/verilatorVerilator open-source SystemVerilog simulator and lint system
C++ GNU Lesser General Public License v3.0 UpdatedFeb 7, 2021 -
OpenSTA Public
Forked from The-OpenROAD-Project/OpenSTAOpenSTA engine
C++ GNU General Public License v3.0 UpdatedFeb 6, 2021 -
OpenROAD Public
Forked from The-OpenROAD-Project/OpenROADOpenROAD's unified application implementing an RTL-to-GDS Flow
Verilog Other UpdatedFeb 4, 2021 -
iverilog Public
Forked from steveicarus/iverilogIcarus Verilog
C++ GNU General Public License v2.0 UpdatedFeb 1, 2021 -
rocket-chip Public
Forked from chipsalliance/rocket-chipRocket Chip Generator
Scala Other UpdatedOct 10, 2018 -
riscv-gnu-toolchain Public
Forked from riscv-collab/riscv-gnu-toolchainGNU toolchain for RISC-V, including GCC
C Other UpdatedOct 9, 2018 -
riscv-boom Public
Forked from riscv-boom/riscv-boomBerkeley Out-of-Order Machine
Scala Other UpdatedOct 5, 2018 -
boom-template Public
Forked from esperantotech/boom-templateA template for building new projects/platforms using the BOOM core.
Shell Other UpdatedSep 27, 2018 -
freedom Public
Forked from sifive/freedomSource files for SiFive's Freedom platforms
Scala Apache License 2.0 UpdatedAug 28, 2018 -
miaow Public
Forked from VerticalResearchGroup/miaowAn open source GPU based off of the AMD Southern Islands ISA.
Verilog BSD 3-Clause "New" or "Revised" License UpdatedSep 25, 2017