Incorporate Andy Glew's comments

The RVWMO is version 2.0 (riscv#483)

The preface says the RVWMO is version 2.0 and has been ratified, but the text
of the standard still says it's version 0.1.

Signed-off-by: Palmer Dabbelt <[email protected]>

Update chapters 2 and 7 for Hypervisor v0.6

Update hypervisor spec to v0.6

h/t @jhauser-us, as usual

Clarify mvendorid.Bank vs. JEDEC bank number

Resolves riscv#468

ignore write to "controlled" SBE and UBE. (riscv#477)

* ignore write to "controlled" SBE and UBE.

Behaviour when endian fields are hard-coupled is not well defined.
If both fields are written with opposite endianness which takes precedence,
 or are the fields left unchanged?
Both approaches are currently used in CSRs.
Further complicating the situation on RV32 systems is the separation
of UBE from MBE/SBE into two CSRs.
Whereas precedence and conflict cannot be determined for two discrete CSR
 updates I propose instead that controlled fields not be directly writable.

Signed-off-by: David Horner <[email protected]>

* fix typo to  ignore write to "controlled" SBE and UBE.

Signed-off-by: David Horner <[email protected]>

Correct left double quotes (riscv#475)

Add Western Digital's SweRV EL2 and EH2 cores (riscv#474)

Western Digital's second generation cores SweRV EL2 and EH2

Clarified that NMIs are interrupts, and should set mcause to have hig…

…h bit set.

Exception code of zero should be returned for systems that don't distinguish NMI or when cause is unknown.
This is not backwards-incompatible given that NMI mcause value was always specified as implementation-defined.
Closes riscv#473.

Fix PDF searching by changing e.g. {\em x}\,IE to {\em x}\/IE

Resolves riscv#447