Resolve package types in interfaces (YosysHQ#3658)

* Resolve package types in interfaces * Added test for resolving of package types in interfaces
povik · Feb 12, 2023 · 615adc4 · 615adc4
1 parent 5ea2c29
commit 615adc4
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Showing 4 changed files with 34 additions and 3 deletions.
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
@@ -1016,7 +1016,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 	// create name resolution entries for all objects with names
 	// also merge multiple declarations for the same wire (e.g. "output foobar; reg foobar;")
-	if (type == AST_MODULE) {
+	if (type == AST_MODULE || type == AST_INTERFACE) {
 		current_scope.clear();
 		std::set<std::string> existing;
 		int counter = 0;
@@ -1701,7 +1701,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 	current_filename = filename;
 
-	if (type == AST_MODULE)
+	if (type == AST_MODULE || type == AST_INTERFACE)
 		current_scope.clear();
 
 	// convert defparam nodes to cell parameters
@@ -4691,7 +4691,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
 	if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic)))
 		mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
 
-	if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))
+	if ((type == AST_MODULE || type == AST_INTERFACE) && get_bool_attribute(ID::mem2reg))
 		children_flags |= AstNode::MEM2REG_FL_ALL;
 
 	dict<AstNode*, uint32_t> *proc_flags_p = NULL;

diff --git a/tests/svinterfaces/resolve_types.sv b/tests/svinterfaces/resolve_types.sv
@@ -0,0 +1,24 @@
+// This test checks that types, including package types, are resolved from within an interface.
+
+typedef logic [7:0] x_t;
+
+package pkg;
+    typedef logic [7:0] y_t;
+endpackage
+
+interface iface;
+    x_t x;
+    pkg::y_t y;
+endinterface
+
+module dut (input logic [7:0] x, output logic [7:0] y);
+  iface intf();
+  assign intf.x = x;
+  assign y = intf.y;
+
+  ondemand u(.intf);
+endmodule
+
+module ref (input logic [7:0] x, output logic [7:0] y);
+  assign y = ~x;
+endmodule
diff --git a/tests/svinterfaces/resolve_types.ys b/tests/svinterfaces/resolve_types.ys
@@ -0,0 +1,6 @@
+read_verilog -sv resolve_types.sv
+hierarchy -libdir . -check
+flatten
+equiv_make ref dut equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh
@@ -4,3 +4,4 @@
 ./runone.sh  svinterface_at_top
 
 ./run_simple.sh load_and_derive
+./run_simple.sh resolve_types
Original file line number	Diff line number	Diff line change
Expand Up		@@ -4,3 +4,4 @@
		./runone.sh svinterface_at_top

		./run_simple.sh load_and_derive
		./run_simple.sh resolve_types