Merge pull request YosysHQ#3552 from daglem/fix-sv-c-array-dimensions

Correct interpretation of SystemVerilog C-style array dimensions
povik · Nov 23, 2022 · fc2f622 · fc2f622
2 parents 13e4f34 + a862642
commit fc2f622
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
@@ -229,9 +229,9 @@ static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
 static void rewriteRange(AstNode *rangeNode)
 {
 	if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
-		// SV array size [n], rewrite as [n-1:0]
-		rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
-		rangeNode->children.push_back(AstNode::mkconst_int(0, false));
+		// SV array size [n], rewrite as [0:n-1]
+		rangeNode->children.push_back(new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)));
+		rangeNode->children[0] = AstNode::mkconst_int(0, false);
 	}
 }