An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.

Experimental flows using nextpnr for Xilinx devices

Structural Netlist API (and more) for EDA post synthesis flow development

Personal Active Dosimeter (PAD) training model with optional Dosimeter Display Unit (DDU). The system safely simulates radiation exposure without real hazards.

Incremental Model Checking Toolkit

Eclipse Layout Kernel - Automatic layout for Java applications.

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.

Logic circuit analysis and optimization

CX2388x direct ADC capture driver, updated for Linux 3.x+ and 64-bit

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

XCircuit circuit drawing and schematic capture tool

CaDiCaL SAT Solver

UAV GNSS navigation module with RTK capability.

Verified Software Toolchain

TestFloat release 3

slang-based frontend for Yosys

mimalloc is a compact general purpose allocator with excellent performance.

SystemVerilog compiler and language services

Cryptol: The Language of Cryptography

Lower Size Bounds for Sorting Networks

WebAssembly soft-core

Symbolic execution of LLVM IR

ThunderFly mobile ground control station

In-Variants with Yosys

draws an SVG schematic from a JSON netlist

Majority-inverter graph based logic optimiser (highly experimental)

Automatic aerotowing unmanned aircraft (UAV) for sport glider or cargo glider towing

lightweight open HLS for FPGA rapid prototyping

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.