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  • sweden Public

    Updated Oct 3, 2024

  • riscv Public

    Forked from openhwgroup/cv32e40p

    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

    SystemVerilog Other Updated Jul 22, 2019

  • bootstrap Public

    Forked from twbs/bootstrap

    The most popular HTML, CSS, and JavaScript framework for developing responsive, mobile first projects on the web.

    JavaScript MIT License Updated Mar 25, 2019

  • test_git Public

    Other Updated Mar 25, 2019

  • fft_simd Public

    Forked from jagger2048/fft_simd

    A simple demo shows how to use the SIMD,Single Instruction Multiple Data, to optimize and accelerate the FFT algorithm.

    C++ Updated Feb 19, 2019

  • fpu Public

    Forked from dawsonjon/fpu

    synthesiseable ieee 754 floating point library in verilog

    Verilog MIT License Updated Jan 21, 2019

  • vim-expand-region Public

    Forked from terryma/vim-expand-region

    Vim plugin that allows you to visually select increasingly larger regions of text using the same key combination.

    Vim Script MIT License Updated Nov 1, 2017

  • hello-github Public

    Just a test repository

    C Updated Apr 20, 2016

  • r22sdf Public

    Forked from ataddei/r22sdf

    MyHDL design of a R2²SDF FFT

    Python Updated Apr 27, 2015