kasli: add spiflash2x

pypga · Jan 5, 2018 · c6ffa44 · c6ffa44
1 parent 13494eb
commit c6ffa44
Showing 1 changed file with 10 additions and 0 deletions.
diff --git a/migen/build/platforms/sinara/kasli.py b/migen/build/platforms/sinara/kasli.py
@@ -42,6 +42,16 @@
         IOStandard("LVCMOS25")
     ),
 
+    ("spiflash2x", 0,
+        Subsignal("cs_n", Pins("T19")),
+        Subsignal("dq", Pins("P22 R22")),
+        Subsignal("wp", Pins("P21")),
+        Subsignal("hold", Pins("R21")),
+        # "clk" is on CCLK
+        IOStandard("LVCMOS25")
+    ),
+
+
     ("clk_gtp", 0,
         Subsignal("p", Pins("F6")),
         Subsignal("n", Pins("E6")),