-
cocotb Public
Forked from cocotb/cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Python BSD 3-Clause "New" or "Revised" License UpdatedJul 4, 2024 -
FPGA-SATA-HBA Public
Forked from WangXuan95/FPGA-SATA-HBAA SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。
SystemVerilog GNU General Public License v3.0 UpdatedSep 14, 2023 -
Xilinx_Library Public
Forked from suisuisi/FPGA_LibraryVivado诸多IP,包括图像处理等
Ada MIT License UpdatedAug 13, 2023 -
ebook-GPT-translator Public
Forked from jesselau76/ebook-GPT-translatorEnjoy reading with your favorite style.
Python MIT License UpdatedApr 23, 2023 -
x393 Public
Forked from Elphel/x393mirror of https://git.elphel.com/Elphel/x393
Verilog GNU General Public License v3.0 UpdatedMar 16, 2023 -
xkISP Public
Forked from openasic-org/xkISPxkISP:Xinkai ISP IP Core (HLS)
Verilog Other UpdatedMar 14, 2023 -
ISP-pipeline-hdrplus Public
Forked from jhfmat/ISP-pipeline-hdrplusDenoise,HDR,Isppipeline,Image-processing(图形处理),camera, Isp ,HDRplus
C UpdatedMar 9, 2023 -
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
SystemVerilog Apache License 2.0 UpdatedFeb 16, 2023 -
basic_verilog Public
Forked from pConst/basic_verilogMust-have verilog systemverilog modules
Verilog UpdatedFeb 5, 2023 -
AutoBridge Public
Forked from UCLA-VAST/AutoBridge[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
C++ MIT License UpdatedJan 3, 2023 -
-
zynqmp_cam_isp_demo Public
Forked from bxinquan/zynqmp_cam_isp_demoISP-Lite, VIP, MIPI-RX IP实现,测试平台为KV260+AR1335 3MP@30fps
VHDL MIT License UpdatedDec 18, 2022 -
edalize Public
Forked from olofk/edalizeAn abstraction library for interfacing EDA tools
Python BSD 2-Clause "Simplified" License UpdatedNov 21, 2022 -
fxpmath Public
Forked from francof2a/fxpmathA python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
Python MIT License UpdatedNov 10, 2022 -
fusesoc Public
Forked from olofk/fusesocPackage manager and build abstraction tool for FPGA/ASIC development
Python BSD 2-Clause "Simplified" License UpdatedOct 31, 2022 -
qspiflash Public
Forked from ZipCPU/qspiflashA set of Wishbone Controlled SPI Flash Controllers
Verilog UpdatedOct 31, 2022 -
FPGA-ftdi245fifo Public
Forked from WangXuan95/FPGA-ftdi245fifoFPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。
SystemVerilog UpdatedOct 27, 2022 -
FPGA-USB-Device Public
Forked from WangXuan95/FPGA-USB-DeviceAn FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-disk, USB-keyboard, etc. It requires 3 common IOs instead of additional chips. 基于FPGA的USB full-speed dev…
SystemVerilog UpdatedOct 25, 2022 -
axi Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog Other UpdatedOct 7, 2022 -
riffa Public
Forked from KastnerRG/riffaThe RIFFA development repository
Verilog Other UpdatedSep 30, 2022 -
pp4fpgas-cn Public
Forked from xupsh/pp4fpgas-cn中文版 Parallel Programming for FPGAs
CSS UpdatedSep 30, 2022 -
open-register-design-tool Public
Forked from Juniper/open-register-design-toolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
Verilog Apache License 2.0 UpdatedSep 4, 2022 -
AXI-SDCard-High-Speed-Controller Public
Forked from lizhirui/AXI-SDCard-High-Speed-ControllerA SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
SystemVerilog Apache License 2.0 UpdatedAug 29, 2022 -
typer Public
Forked from fastapi/typerTyper, build great CLIs. Easy to code. Based on Python type hints.
Python MIT License UpdatedAug 25, 2022 -
PYNQ Public
Forked from Xilinx/PYNQPython Productivity for ZYNQ
Jupyter Notebook BSD 3-Clause "New" or "Revised" License UpdatedAug 17, 2022 -
cdbus_ip Public
Forked from dukelec/cdbusCDBUS Protocol and the IP Core for FPGA users
Verilog UpdatedAug 8, 2022 -
verilog-pcie Public
Forked from alexforencich/verilog-pcieVerilog PCI express components
Verilog MIT License UpdatedAug 1, 2022 -
-
verilog-ethernet Public
Forked from alexforencich/verilog-ethernetVerilog Ethernet components for FPGA implementation
Verilog MIT License UpdatedJul 25, 2022 -
verilog-axis Public
Forked from alexforencich/verilog-axisVerilog AXI stream components for FPGA implementation
Python MIT License UpdatedMay 16, 2022