opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.

Convolutional accelerator kernel, target ASIC & FPGA

Small-scale Tensor Processing Unit built on an FPGA

The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

同济大学22级数字逻辑大作业