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2-stage is updated to the new Privileged Spec v1.7.
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@ccelio
ccelio committed Jul 3, 2015
1 parent f0bd776 commit 0e093da
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Showing 4 changed files with 103 additions and 60 deletions.
6 changes: 1 addition & 5 deletions src/rv32_2stage/consts.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@ trait ScalarOpConstants
val PC_BR = UInt(1, 3) // branch_target
val PC_J = UInt(2, 3) // jump_target
val PC_JR = UInt(3, 3) // jump_reg_target
val PC_EXC = UInt(4, 3) // exception

// Branch Type
val BR_N = UInt(0, 4) // Next
Expand Down Expand Up @@ -107,11 +108,6 @@ trait ScalarOpConstants
val MSK_HU = UInt(3, 3)
val MSK_W = UInt(4, 3)
val MSK_X = UInt(4, 3)

// Enable Co-processor Register Signal (ToHost Register, etc.)
val PCR_N = UInt(0,2)
val PCR_F = UInt(1,2)
val PCR_T = UInt(2,2)
}

}
Expand Down
100 changes: 66 additions & 34 deletions src/rv32_2stage/cpath.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,20 +14,23 @@ import Common._
import Common.Instructions._
import Constants._

class CtlToDatIo extends Bundle()
class CtlToDatIo extends Bundle()
{
val stall = Bool(OUTPUT)
val if_kill = Bool(OUTPUT)
val if_kill = Bool(OUTPUT)
val pc_sel = UInt(OUTPUT, 3)
val op1_sel = UInt(OUTPUT, 2)
val op2_sel = UInt(OUTPUT, 3)
val alu_fun = UInt(OUTPUT, 5)
val wb_sel = UInt(OUTPUT, 2)
val rf_wen = Bool(OUTPUT)
val csr_cmd = UInt(OUTPUT, 2)
val rf_wen = Bool(OUTPUT)
val csr_cmd = UInt(OUTPUT, CSR.SZ)

val exception = Bool(OUTPUT)
val exc_cause = UInt(OUTPUT, 32)
}

class CpathIo(implicit conf: SodorConfiguration) extends Bundle()
class CpathIo(implicit conf: SodorConfiguration) extends Bundle()
{
val imem = new MemPortIo(conf.xprlen)
val dmem = new MemPortIo(conf.xprlen)
Expand All @@ -40,8 +43,8 @@ class CtlPath(implicit conf: SodorConfiguration) extends Module
{
val io = new CpathIo();

val csignals =
ListLookup(io.dat.inst,
val csignals =
ListLookup(io.dat.inst,
List(N, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X ,MT_X, CSR.N),
Array( /* val | BR | op1 | op2 | ALU | wb | rf | mem | mem | mask | csr */
/* inst | type | sel | sel | fcn | sel | wen | en | wr | type | cmd */
Expand All @@ -53,10 +56,10 @@ class CtlPath(implicit conf: SodorConfiguration) extends Module
SW -> List(Y, BR_N , OP1_RS1, OP2_IMS , ALU_ADD , WB_X , REN_0, MEN_1, M_XWR, MT_W, CSR.N),
SB -> List(Y, BR_N , OP1_RS1, OP2_IMS , ALU_ADD , WB_X , REN_0, MEN_1, M_XWR, MT_B, CSR.N),
SH -> List(Y, BR_N , OP1_RS1, OP2_IMS , ALU_ADD , WB_X , REN_0, MEN_1, M_XWR, MT_H, CSR.N),

AUIPC -> List(Y, BR_N , OP1_IMU, OP2_PC , ALU_ADD ,WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
LUI -> List(Y, BR_N , OP1_IMU, OP2_X , ALU_COPY1,WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),

ADDI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
ANDI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_AND , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
ORI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_OR , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
Expand All @@ -66,7 +69,7 @@ class CtlPath(implicit conf: SodorConfiguration) extends Module
SLLI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRAI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRLI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),

SLL -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
ADD -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SUB -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SUB , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
Expand All @@ -77,7 +80,7 @@ class CtlPath(implicit conf: SodorConfiguration) extends Module
XOR -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_XOR , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRA -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRL -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),

JAL -> List(Y, BR_J , OP1_X , OP2_X , ALU_X , WB_PC4, REN_1, MEN_0, M_X , MT_X, CSR.N),
JALR -> List(Y, BR_JR , OP1_RS1, OP2_IMI , ALU_X , WB_PC4, REN_1, MEN_0, M_X , MT_X, CSR.N),
BEQ -> List(Y, BR_EQ , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N),
Expand All @@ -86,38 +89,51 @@ class CtlPath(implicit conf: SodorConfiguration) extends Module
BGEU -> List(Y, BR_GEU, OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N),
BLT -> List(Y, BR_LT , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N),
BLTU -> List(Y, BR_LTU, OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N),

CSRRWI -> List(Y, BR_N , OP1_IMZ, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.W),
CSRRSI -> List(Y, BR_N , OP1_IMZ, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.S),
CSRRW -> List(Y, BR_N , OP1_RS1, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.W),
CSRRS -> List(Y, BR_N , OP1_RS1, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.S)
CSRRS -> List(Y, BR_N , OP1_RS1, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.S),
CSRRC -> List(Y, BR_N , OP1_RS1, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.C),
CSRRCI -> List(Y, BR_N , OP1_IMZ, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.C),

SCALL -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.I),
SRET -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.I),
MRTS -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.I),
SBREAK -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.I),
WFI -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N), // implemented as a NOP

FENCE_I-> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N),
FENCE -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_1, M_X , MT_X, CSR.N)
// we are already sequentially consistent, so no need to honor the fence instruction

))

// Put these control signals in variables
val (cs_val_inst: Bool) :: cs_br_type :: cs_op1_sel :: cs_op2_sel :: cs_alu_fun :: cs_wb_sel :: cs0 = csignals
val (cs_rf_wen: Bool) :: (cs_mem_en: Bool) :: cs_mem_fcn :: cs_msk_sel :: cs_csr_cmd :: Nil = cs0


// Branch Logic
val ctrl_pc_sel
= Lookup(cs_br_type, UInt(0, 3),
Array( BR_N -> PC_4,
BR_NE -> Mux(!io.dat.br_eq, PC_BR, PC_4),
BR_EQ -> Mux( io.dat.br_eq, PC_BR, PC_4),
BR_GE -> Mux(!io.dat.br_lt, PC_BR, PC_4),
BR_GEU-> Mux(!io.dat.br_ltu, PC_BR, PC_4),
BR_LT -> Mux( io.dat.br_lt, PC_BR, PC_4),
BR_LTU-> Mux( io.dat.br_ltu, PC_BR, PC_4),
BR_J -> PC_J,
BR_JR -> PC_JR
));

// Branch Logic
val ctrl_pc_sel = Mux(io.ctl.exception ||
io.dat.csr_eret ||
io.dat.csr_xcpt , PC_EXC,
Mux(cs_br_type === BR_N , PC_4,
Mux(cs_br_type === BR_NE , Mux(!io.dat.br_eq, PC_BR, PC_4),
Mux(cs_br_type === BR_EQ , Mux( io.dat.br_eq, PC_BR, PC_4),
Mux(cs_br_type === BR_GE , Mux(!io.dat.br_lt, PC_BR, PC_4),
Mux(cs_br_type === BR_GEU, Mux(!io.dat.br_ltu, PC_BR, PC_4),
Mux(cs_br_type === BR_LT , Mux( io.dat.br_lt, PC_BR, PC_4),
Mux(cs_br_type === BR_LTU, Mux( io.dat.br_ltu, PC_BR, PC_4),
Mux(cs_br_type === BR_J , PC_J,
Mux(cs_br_type === BR_JR , PC_JR,
PC_4))))))))))

// stall entire pipeline on I$ or D$ miss
val stall = !io.imem.resp.valid || !((cs_mem_en && io.dmem.resp.valid) || !cs_mem_en)
val ifkill = !(ctrl_pc_sel === PC_4)

val ifkill = !(ctrl_pc_sel === PC_4)

io.ctl.stall := stall
io.ctl.if_kill := ifkill
io.ctl.pc_sel := ctrl_pc_sel
Expand All @@ -126,16 +142,32 @@ class CtlPath(implicit conf: SodorConfiguration) extends Module
io.ctl.alu_fun := cs_alu_fun
io.ctl.wb_sel := cs_wb_sel
io.ctl.rf_wen := Mux(stall, Bool(false), cs_rf_wen)
io.ctl.csr_cmd := Mux(stall, PCR_N, cs_csr_cmd)



// convert CSR instructions with raddr1 == 0 to read-only CSR commands
val rs1_addr = io.dat.inst(RS1_MSB, RS1_LSB)
val csr_ren = (cs_csr_cmd === CSR.S || cs_csr_cmd === CSR.C) && rs1_addr === UInt(0)
val csr_cmd = Mux(csr_ren, CSR.R, cs_csr_cmd)

io.ctl.csr_cmd := Mux(stall, CSR.N, csr_cmd)

io.imem.req.valid := Bool(true)
io.imem.req.bits.fcn := M_XRD
io.imem.req.bits.typ := MT_WU

io.dmem.req.valid := cs_mem_en
io.dmem.req.bits.fcn := cs_mem_fcn
io.dmem.req.bits.typ := cs_msk_sel

io.dmem.req.bits.typ := cs_msk_sel


// Exception Handling ---------------------

val exc_illegal = (!cs_val_inst && io.imem.resp.valid)

io.ctl.exception := exc_illegal || io.dat.csr_interrupt
io.ctl.exc_cause := Mux(io.dat.csr_interrupt, io.dat.csr_interrupt_cause,
UInt(Common.Causes.illegal_instruction))

}

}
56 changes: 36 additions & 20 deletions src/rv32_2stage/dpath.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,12 +15,16 @@ import Constants._
import Common._
import Common.Constants._

class DatToCtlIo extends Bundle()
class DatToCtlIo(implicit conf: SodorConfiguration) extends Bundle()
{
val inst = Bits(OUTPUT, 32)
val br_eq = Bool(OUTPUT)
val br_lt = Bool(OUTPUT)
val br_ltu= Bool(OUTPUT)
val csr_eret = Bool(OUTPUT)
val csr_interrupt = Bool(OUTPUT)
val csr_xcpt = Bool(OUTPUT)
val csr_interrupt_cause = UInt(OUTPUT, conf.xprlen)
}

class DpathIo(implicit conf: SodorConfiguration) extends Bundle()
Expand Down Expand Up @@ -50,6 +54,7 @@ class DatPath(implicit conf: SodorConfiguration) extends Module
val exe_br_target = UInt()
val exe_jmp_target = UInt()
val exe_jump_reg_target = UInt()
val exception_target = UInt()

when (!io.ctl.stall)
{
Expand All @@ -62,7 +67,8 @@ class DatPath(implicit conf: SodorConfiguration) extends Module
(io.ctl.pc_sel === PC_4) -> if_pc_plus4,
(io.ctl.pc_sel === PC_BR) -> exe_br_target,
(io.ctl.pc_sel === PC_J ) -> exe_jmp_target,
(io.ctl.pc_sel === PC_JR) -> exe_jump_reg_target
(io.ctl.pc_sel === PC_JR) -> exe_jump_reg_target,
(io.ctl.pc_sel === PC_EXC)-> exception_target
))

//Instruction Memory
Expand Down Expand Up @@ -98,7 +104,7 @@ class DatPath(implicit conf: SodorConfiguration) extends Module
// Register File
val regfile = Mem(Bits(width = conf.xprlen), 32)

when (io.ctl.rf_wen && (exe_wbaddr != UInt(0)))
when (io.ctl.rf_wen && (exe_wbaddr != UInt(0)) && !io.dat.csr_xcpt)
{
regfile(exe_wbaddr) := exe_wbdata
}
Expand Down Expand Up @@ -164,18 +170,24 @@ class DatPath(implicit conf: SodorConfiguration) extends Module

// Control Status Registers
val csr = Module(new CSRFile())
val csr_cmd = io.ctl.csr_cmd
csr.io.host <> io.host
csr.io.rw.addr := exe_reg_inst(CSR_ADDR_MSB,CSR_ADDR_LSB)
csr.io.rw.wdata := Mux(csr_cmd=== CSR.S, csr.io.rw.rdata | exe_alu_out,
Mux(csr_cmd=== CSR.C, csr.io.rw.rdata & ~exe_alu_out,
exe_alu_out))
csr.io.rw.cmd := csr_cmd
csr.io.rw.cmd := io.ctl.csr_cmd
csr.io.rw.wdata := exe_alu_out
val csr_out = csr.io.rw.rdata

csr.io.retire := Bool(false) // TODO
csr.io.exception := Bool(false) // no supervisor mode supported

csr.io.retire := !io.ctl.stall // TODO verify this works properly
csr.io.exception := io.ctl.exception
csr.io.cause := io.ctl.exc_cause
csr.io.pc := exe_reg_pc
exception_target := csr.io.evec

io.dat.csr_eret := csr.io.eret
io.dat.csr_xcpt := csr.io.csr_xcpt
io.dat.csr_interrupt := csr.io.interrupt
io.dat.csr_interrupt_cause := csr.io.interrupt_cause
// TODO replay? stall?

// Add your own uarch counters here!
csr.io.uarch_counters.foreach(_ := Bool(false))

Expand Down Expand Up @@ -210,25 +222,29 @@ class DatPath(implicit conf: SodorConfiguration) extends Module


// Printout
printf("Cyc= %d PC= (0x%x,0x%x) [%s,%s] Exe: %s %s%s%s Op1=[0x%x] Op2=[0x%x] W[%s,%d= 0x%x]\n"
// TODO: provide a way to provide a disassembly on just the opcode.
// left as "n/a" for now.
printf("Cyc= %d Op1=[0x%x] Op2=[0x%x] W[%s,%d= 0x%x] PC= (0x%x,0x%x) [%x,%x] %s%s%s Exe: DASM(%x)\n"
, tsc_reg(31,0)
, exe_alu_op1
, exe_alu_op2
, Mux(io.ctl.rf_wen, Str("W"), Str("_"))
, exe_wbaddr
, exe_wbdata
, if_reg_pc
, exe_reg_pc
, Disassemble(if_inst, true)
, Disassemble(exe_reg_inst, true)
, Disassemble(exe_reg_inst)
// , Disassemble(if_inst, true)
// , Disassemble(exe_reg_inst, true)
, if_inst(6,0)
, exe_reg_inst(6,0)
, Mux(io.ctl.stall, Str("stall"), Str(" "))
, Mux(io.ctl.if_kill, Str("KILL"), Str(" "))
, Mux(io.ctl.pc_sel === UInt(1), Str("BR"),
Mux(io.ctl.pc_sel === UInt(2), Str("J "),
Mux(io.ctl.pc_sel === UInt(3), Str("JR"),
Mux(io.ctl.pc_sel === UInt(4), Str("EX"),
Mux(io.ctl.pc_sel === UInt(0), Str(" "), Str("??"))))))
, exe_alu_op1
, exe_alu_op2
, Mux(io.ctl.rf_wen, Str("W"), Str("_"))
, exe_wbaddr
, exe_wbdata
, exe_reg_inst
)
}

Expand Down
1 change: 0 additions & 1 deletion src/rv32_2stage/package.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,6 @@ object Constants extends
SodorProcConstants with
ScalarOpConstants with
Common.constants.RISCVConstants with
Common.constants.ExcCauseConstants with
Common.MemoryOpConstants
{
}

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