add tracer back into 1 and 5 stage

qicny · Jan 24, 2016 · a5e0cc2 · a5e0cc2
1 parent da24c29
commit a5e0cc2
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Showing 5 changed files with 44 additions and 20 deletions.
diff --git a/.gitignore b/.gitignore
@@ -14,4 +14,5 @@ install/share
 *.vpd
 .DS_Store
 sbt/*/target
+*/target
 *.log
diff --git a/emulator/rv32_1stage/emulator.cpp b/emulator/rv32_1stage/emulator.cpp
@@ -3,6 +3,7 @@
 #include "emulator.h"
 //#include "disasm.h" // disabled for now... need to update to the current ISA/ABI in common/disasm.*
 #include "Top.h" // chisel-generated code...
+#include "tracer.h"
 #include <fcntl.h>
 #include <signal.h>
 #include <stdio.h>
@@ -59,12 +60,16 @@ int main(int argc, char** argv)
       fprintf(vcdfile, "$var reg 64 NCYCLE cycle $end\n");
       fprintf(vcdfile, "$upscope $end\n");
    }
- 
+
    // The chisel generated code
    Top_t dut; // design under test, aka, your chisel code
    srand(random_seed);
    dut.init(random_seed != 0);
-
+
+   Tracer_t tracer(&dut.Top_tile_core_d__inst,
+                   &dut.Top_tile_core_d_csr__reg_stats,
+                   stderr);
+
    if (loadmem)
    {
       //  mem_t<32,32768> Top_tile_memory__data_bank1;
@@ -75,7 +80,7 @@ int main(int argc, char** argv)
          std::cerr << "could not open " << loadmem<< std::endl;
          exit(-1);
       }
- 
+
 
       std::string line;
       uint64_t mem_idx = 0; // unit is 4-byte words
@@ -135,6 +140,8 @@ int main(int argc, char** argv)
       dut.clock_hi(LIT<1>(1));
    }
 
+   tracer.start();
+
    while (!htif->done())
    {
       dut.clock_lo(LIT<1>(0));
@@ -167,8 +174,9 @@ int main(int argc, char** argv)
       dut.Top__io_htif_mem_req_bits_rw = htif->mem_req_bits_rw;
 
       dut.Top__io_htif_reset = htif->reset;
-
-
+
+      tracer.tick(true);
+
       if (log || vcd)
       {
          if (log)
@@ -200,6 +208,9 @@ int main(int argc, char** argv)
       }
    }
 
+   tracer.stop();
+   tracer.print();
+
    if (vcd)
       fclose(vcdfile);
 

diff --git a/emulator/rv32_5stage/emulator.cpp b/emulator/rv32_5stage/emulator.cpp
@@ -3,6 +3,7 @@
 #include "emulator.h"
 //#include "disasm.h"
 #include "Top.h" // chisel-generated code...
+#include "tracer.h"
 #include <fcntl.h>
 #include <signal.h>
 #include <stdio.h>
@@ -60,12 +61,16 @@ int main(int argc, char** argv)
       fprintf(vcdfile, "$var reg 64 NCYCLE cycle $end\n");
       fprintf(vcdfile, "$upscope $end\n");
    }
- 
+
    // The chisel generated code
    Top_t dut; // design under test, aka, your chisel code
    srand(random_seed);
    dut.init(random_seed != 0);
-
+
+   Tracer_t tracer(&dut.Top_tile_core_d__exe_reg_inst,
+                   &dut.Top_tile_core_d_csr__reg_stats,
+                   stderr);
+
    if (loadmem)
    {
       //  mem_t<32,32768> Top_tile_memory__data_bank1;
@@ -76,7 +81,7 @@ int main(int argc, char** argv)
          std::cerr << "could not open " << loadmem<< std::endl;
          exit(-1);
       }
- 
+
 
       std::string line;
       uint64_t mem_idx = 0; // unit is 4-byte words
@@ -91,9 +96,9 @@ int main(int argc, char** argv)
          #define parse_nibble(c) ((c) >= 'a' ? (c)-'a'+10 : (c)-'0')
          for (ssize_t i = line.length()-2, j = 0; i >= 0; i -= 2, j++)
          {
-            uint8_t byte = (parse_nibble(line[i]) << 4) | parse_nibble(line[i+1]); 
+            uint8_t byte = (parse_nibble(line[i]) << 4) | parse_nibble(line[i+1]);
             m[j>>2] = (byte << ((j%4)*8)) | m[j>>2];
-            
+
 //            fprintf(stderr,"byte: j=%d, byte=0x%x, m[j>>2=%d]=0x%x\n", j, byte, (j>>2), m[j>>2]);
          }
 
@@ -133,6 +138,8 @@ int main(int argc, char** argv)
       dut.clock_hi(LIT<1>(1));
    }
 
+   tracer.start();
+
    while (!htif->done())
    {
       dut.clock_lo(LIT<1>(0));
@@ -164,7 +171,9 @@ int main(int argc, char** argv)
       dut.Top__io_htif_mem_req_bits_rw = htif->mem_req_bits_rw;
 
       dut.Top__io_htif_reset = htif->reset;
-
+
+      tracer.tick(true);
+
       if (log || vcd)
       {
          if (log)
@@ -196,6 +205,9 @@ int main(int argc, char** argv)
       }
    }
 
+   tracer.stop();
+   tracer.print();
+
    if (vcd)
       fclose(vcdfile);
 

diff --git a/riscv-fesvr b/riscv-fesvr
diff --git a/src/rv32_1stage/dpath.scala b/src/rv32_1stage/dpath.scala
@@ -106,28 +106,28 @@ class DatPath(implicit conf: SodorConfiguration) extends Module
    val imm_b_sext = Cat(Fill(imm_b(11), 19), imm_b, UInt(0))
    val imm_u_sext = Cat(imm_u, Fill(UInt(0), 12))
    val imm_j_sext = Cat(Fill(imm_j(19), 11), imm_j, UInt(0))
-   
-   
+
+
    val alu_op1 = MuxCase(UInt(0), Array(
                (io.ctl.op1_sel === OP1_RS1) -> rs1_data,
                (io.ctl.op1_sel === OP1_IMU) -> imm_u_sext,
                (io.ctl.op1_sel === OP1_IMZ) -> imm_z
                )).toUInt
-   
+
    val alu_op2 = MuxCase(UInt(0), Array(
                (io.ctl.op2_sel === OP2_RS2) -> rs2_data,
                (io.ctl.op2_sel === OP2_PC)  -> pc_reg,
                (io.ctl.op2_sel === OP2_IMI) -> imm_i_sext,
                (io.ctl.op2_sel === OP2_IMS) -> imm_s_sext
                )).toUInt
- 
- 
+
+
 
    // ALU
    val alu_out   = UInt(width = conf.xprlen)
-   
+
    val alu_shamt = alu_op2(4,0).toUInt
-   
+
    alu_out := MuxCase(UInt(0), Array(
                   (io.ctl.alu_fun === ALU_ADD)  -> (alu_op1 + alu_op2).toUInt,
                   (io.ctl.alu_fun === ALU_SUB)  -> (alu_op1 - alu_op2).toUInt,
@@ -146,7 +146,7 @@ class DatPath(implicit conf: SodorConfiguration) extends Module
    br_target       := pc_reg + imm_b_sext
    jmp_target      := pc_reg + imm_j_sext
    jump_reg_target := (rs1_data.toUInt + imm_i_sext.toUInt)
-                                  
+
    // Control Status Registers
    val csr = Module(new CSRFile())
    csr.io.host <> io.host