RISC-V SoC designed by students in UCAS

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Verilog implementation of the SHA-1 cryptgraphic hash function

Minecraft

The ILA model database

FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks