release v4.12-6

CHANGELOG.md

@@ -1,3 +1,7 @@
+v4.12-5 2017-08-31
+--------------------
+Upgrade to Linux 4.12.10
+
 v4.12-5 2017-08-25
 --------------------
 Upgrade to Linux 4.12.9

aur/PKGBUILD

@@ -2,7 +2,7 @@
 
 pkgbase=linux-samus4
 pkgver=4.12
-pkgrel=5
+pkgrel=6
 arch=('x86_64')
 url="https://github.com/raphael/linux-samus"
 license=('GPL2')

build/linux-4.12.10-ph+_4.12.10-ph+-12.dsc

@@ -0,0 +1,22 @@
+Format: 3.0 (quilt)
+Source: linux-4.12.10-ph+
+Binary: linux-image-4.12.10-ph+, linux-headers-4.12.10-ph+, linux-firmware-image-4.12.10-ph+, linux-libc-dev
+Architecture: any all
+Version: 4.12.10-ph+-12
+Maintainer: Anonymous <[email protected]>
+Homepage: http://www.kernel.org/
+Build-Depends: bc, kmod, cpio
+Package-List:
+ linux-firmware-image-4.12.10-ph+ deb kernel optional arch=all
+ linux-headers-4.12.10-ph+ deb kernel optional arch=any
+ linux-image-4.12.10-ph+ deb kernel optional arch=any
+ linux-libc-dev deb devel optional arch=any
+Checksums-Sha1:
+ 54a2cdad55e87a23ba2f796a51e54c292230ec0e 315532895 linux-4.12.10-ph+_4.12.10-ph+.orig.tar.gz
+ a7ed87706b64076b68e6b5b061e2cf63de968291 1251 linux-4.12.10-ph+_4.12.10-ph+-12.debian.tar.gz
+Checksums-Sha256:
+ c7f02b8391d6a2fe583405b9aac3a5963fe958a9d18a68a511808066e6b52690 315532895 linux-4.12.10-ph+_4.12.10-ph+.orig.tar.gz
+ a7abaa8b4ce16eb88852cb4bdbc9386711e263ecad3091064c3840650fdbd0a2 1251 linux-4.12.10-ph+_4.12.10-ph+-12.debian.tar.gz
+Files:
+ 5c129055727dc3aaae553b1f14355cff 315532895 linux-4.12.10-ph+_4.12.10-ph+.orig.tar.gz
+ 0c2939e80faa5cf69253246f40b07f35 1251 linux-4.12.10-ph+_4.12.10-ph+-12.debian.tar.gz

build/linux-4.12.10-ph+_4.12.10-ph+-12_amd64.changes

@@ -0,0 +1,43 @@
+Format: 1.8
+Date: Thu, 31 Aug 2017 20:05:02 -0700
+Source: linux-4.12.10-ph+
+Binary: linux-image-4.12.10-ph+ linux-headers-4.12.10-ph+ linux-firmware-image-4.12.10-ph+ linux-libc-dev
+Architecture: source amd64 all
+Version: 4.12.10-ph+-12
+Distribution: vivid
+Urgency: low
+Maintainer: Anonymous <[email protected]>
+Changed-By: Anonymous <[email protected]>
+Description:
+ linux-firmware-image-4.12.10-ph+ - Linux kernel firmware, version 4.12.10-ph+
+ linux-headers-4.12.10-ph+ - Linux kernel headers for 4.12.10-ph+ on ${kernel:debarch}
+ linux-image-4.12.10-ph+ - Linux kernel, version 4.12.10-ph+
+ linux-libc-dev - Linux support headers for userspace development
+Changes:
+ linux-4.12.10-ph+ (4.12.10-ph+-12) vivid; urgency=low
+ .
+   * Custom built Linux kernel.
+Checksums-Sha1:
+ 7647172c4936e6507800b7fc50a9581a8c9bf231 1173 linux-4.12.10-ph+_4.12.10-ph+-12.dsc
+ 54a2cdad55e87a23ba2f796a51e54c292230ec0e 315532895 linux-4.12.10-ph+_4.12.10-ph+.orig.tar.gz
+ a7ed87706b64076b68e6b5b061e2cf63de968291 1251 linux-4.12.10-ph+_4.12.10-ph+-12.debian.tar.gz
+ 667993ab2c07afa346e40d144c22296e2df174cf 736562 linux-firmware-image-4.12.10-ph+_4.12.10-ph+-12_amd64.deb
+ 05ac915691bd4431ff53f89e37836e1e4b44b4d1 10676430 linux-headers-4.12.10-ph+_4.12.10-ph+-12_amd64.deb
+ 5b255e8aaa28a9057f90802aae0418069373b755 18540522 linux-image-4.12.10-ph+_4.12.10-ph+-12_amd64.deb
+ cf68656d5c65a21b329baf6aad6df41d30d82c62 941760 linux-libc-dev_4.12.10-ph+-12_amd64.deb
+Checksums-Sha256:
+ 18a982c43fb533b54a1c4d29c8ef1f8418067d01a14224e7fcb3a3e4f91f76d2 1173 linux-4.12.10-ph+_4.12.10-ph+-12.dsc
+ c7f02b8391d6a2fe583405b9aac3a5963fe958a9d18a68a511808066e6b52690 315532895 linux-4.12.10-ph+_4.12.10-ph+.orig.tar.gz
+ a7abaa8b4ce16eb88852cb4bdbc9386711e263ecad3091064c3840650fdbd0a2 1251 linux-4.12.10-ph+_4.12.10-ph+-12.debian.tar.gz
+ 0772ea717d1b3ed4e39cdee4ea0cd67175483f1a8ecc436d16ef520e48b7fb8a 736562 linux-firmware-image-4.12.10-ph+_4.12.10-ph+-12_amd64.deb
+ cb9cf1520d558e4254036c619da5fc17b13986d993bd1a9b48e605b08cd18f9b 10676430 linux-headers-4.12.10-ph+_4.12.10-ph+-12_amd64.deb
+ 446c2a9a9ce9ca04cbbe45b157b6cfee5b5b9d765d8f562196988e08df1133c8 18540522 linux-image-4.12.10-ph+_4.12.10-ph+-12_amd64.deb
+ b81e58f27f04146b6e16147bc2d7d5d27bc3c0e6d1fd0b7196651c76c8452de3 941760 linux-libc-dev_4.12.10-ph+-12_amd64.deb
+Files:
+ a24699acded861592a973116bf747660 1173 kernel optional linux-4.12.10-ph+_4.12.10-ph+-12.dsc
+ 5c129055727dc3aaae553b1f14355cff 315532895 kernel optional linux-4.12.10-ph+_4.12.10-ph+.orig.tar.gz
+ 0c2939e80faa5cf69253246f40b07f35 1251 kernel optional linux-4.12.10-ph+_4.12.10-ph+-12.debian.tar.gz
+ 3f585de3fb149d307f7044a7b8b0df1b 736562 kernel optional linux-firmware-image-4.12.10-ph+_4.12.10-ph+-12_amd64.deb
+ 13cc64fd310a3600020dbd8217ef5623 10676430 kernel optional linux-headers-4.12.10-ph+_4.12.10-ph+-12_amd64.deb
+ 6abdab0f6f019104a38d439637433f02 18540522 kernel optional linux-image-4.12.10-ph+_4.12.10-ph+-12_amd64.deb
+ b82603c3012d9fd834dd25a76ee62b8b 941760 devel optional linux-libc-dev_4.12.10-ph+-12_amd64.deb

build/linux/Makefile

@@ -1,6 +1,6 @@
 VERSION = 4
 PATCHLEVEL = 12
-SUBLEVEL = 9
+SUBLEVEL = 10
 EXTRAVERSION =
 NAME = Fearless Coyote
 

build/linux/arch/arc/include/asm/cache.h

@@ -96,7 +96,9 @@ extern unsigned long perip_base, perip_end;
 #define ARC_REG_SLC_FLUSH	0x904
 #define ARC_REG_SLC_INVALIDATE	0x905
 #define ARC_REG_SLC_RGN_START	0x914
+#define ARC_REG_SLC_RGN_START1	0x915
 #define ARC_REG_SLC_RGN_END	0x916
+#define ARC_REG_SLC_RGN_END1	0x917
 
 /* Bit val in SLC_CONTROL */
 #define SLC_CTRL_DIS		0x001

build/linux/arch/arc/include/asm/mmu.h

@@ -94,6 +94,8 @@ static inline int is_pae40_enabled(void)
 	return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
 }
 
+extern int pae40_exist_but_not_enab(void);
+
 #endif	/* !__ASSEMBLY__ */
 
 #endif

build/linux/arch/arc/mm/cache.c

@@ -665,6 +665,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
 	static DEFINE_SPINLOCK(lock);
 	unsigned long flags;
 	unsigned int ctrl;
+	phys_addr_t end;
 
 	spin_lock_irqsave(&lock, flags);
 
@@ -694,8 +695,19 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
 	 * END needs to be setup before START (latter triggers the operation)
 	 * END can't be same as START, so add (l2_line_sz - 1) to sz
 	 */
-	write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));
-	write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
+	end = paddr + sz + l2_line_sz - 1;
+	if (is_pae40_enabled())
+		write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
+
+	write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
+
+	if (is_pae40_enabled())
+		write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
+
+	write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
+
+	/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
+	read_aux_reg(ARC_REG_SLC_CTRL);
 
 	while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
 
@@ -1111,6 +1123,13 @@ noinline void __init arc_ioc_setup(void)
 	__dc_enable();
 }
 
+/*
+ * Cache related boot time checks/setups only needed on master CPU:
+ *  - Geometry checks (kernel build and hardware agree: e.g. L1_CACHE_BYTES)
+ *    Assume SMP only, so all cores will have same cache config. A check on
+ *    one core suffices for all
+ *  - IOC setup / dma callbacks only need to be done once
+ */
 void __init arc_cache_init_master(void)
 {
 	unsigned int __maybe_unused cpu = smp_processor_id();
@@ -1190,12 +1209,27 @@ void __ref arc_cache_init(void)
 
 	printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
 
-	/*
-	 * Only master CPU needs to execute rest of function:
-	 *  - Assume SMP so all cores will have same cache config so
-	 *    any geomtry checks will be same for all
-	 *  - IOC setup / dma callbacks only need to be setup once
-	 */
 	if (!cpu)
 		arc_cache_init_master();
+
+	/*
+	 * In PAE regime, TLB and cache maintenance ops take wider addresses
+	 * And even if PAE is not enabled in kernel, the upper 32-bits still need
+	 * to be zeroed to keep the ops sane.
+	 * As an optimization for more common !PAE enabled case, zero them out
+	 * once at init, rather than checking/setting to 0 for every runtime op
+	 */
+	if (is_isa_arcv2() && pae40_exist_but_not_enab()) {
+
+		if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE))
+			write_aux_reg(ARC_REG_IC_PTAG_HI, 0);
+
+		if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE))
+			write_aux_reg(ARC_REG_DC_PTAG_HI, 0);
+
+		if (l2_line_sz) {
+			write_aux_reg(ARC_REG_SLC_RGN_END1, 0);
+			write_aux_reg(ARC_REG_SLC_RGN_START1, 0);
+		}
+	}
 }

build/linux/arch/arc/mm/tlb.c

@@ -104,6 +104,8 @@
 /* A copy of the ASID from the PID reg is kept in asid_cache */
 DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
 
+static int __read_mostly pae_exists;
+
 /*
  * Utility Routine to erase a J-TLB entry
  * Caller needs to setup Index Reg (manually or via getIndex)
@@ -784,7 +786,7 @@ void read_decode_mmu_bcr(void)
 		mmu->u_dtlb = mmu4->u_dtlb * 4;
 		mmu->u_itlb = mmu4->u_itlb * 4;
 		mmu->sasid = mmu4->sasid;
-		mmu->pae = mmu4->pae;
+		pae_exists = mmu->pae = mmu4->pae;
 	}
 }
 
@@ -809,6 +811,11 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
 	return buf;
 }
 
+int pae40_exist_but_not_enab(void)
+{
+	return pae_exists && !is_pae40_enabled();
+}
+
 void arc_mmu_init(void)
 {
 	char str[256];
@@ -859,6 +866,9 @@ void arc_mmu_init(void)
 	/* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
 	write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
 #endif
+
+	if (pae40_exist_but_not_enab())
+		write_aux_reg(ARC_REG_TLBPD1HI, 0);
 }
 
 /*

build/linux/arch/arm64/kernel/fpsimd.c

@@ -161,9 +161,11 @@ void fpsimd_flush_thread(void)
 {
 	if (!system_supports_fpsimd())
 		return;
+	preempt_disable();
 	memset(&current->thread.fpsimd_state, 0, sizeof(struct fpsimd_state));
 	fpsimd_flush_task_state(current);
 	set_thread_flag(TIF_FOREIGN_FPSTATE);
+	preempt_enable();
 }
 
 /*

build/linux/arch/powerpc/include/asm/mmu_context.h

@@ -80,9 +80,27 @@ static inline void switch_mm_irqs_off(struct mm_struct *prev,
 				      struct task_struct *tsk)
 {
 	/* Mark this context has been used on the new CPU */
-	if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next)))
+	if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) {
 		cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
 
+		/*
+		 * This full barrier orders the store to the cpumask above vs
+		 * a subsequent operation which allows this CPU to begin loading
+		 * translations for next.
+		 *
+		 * When using the radix MMU that operation is the load of the
+		 * MMU context id, which is then moved to SPRN_PID.
+		 *
+		 * For the hash MMU it is either the first load from slb_cache
+		 * in switch_slb(), and/or the store of paca->mm_ctx_id in
+		 * copy_mm_to_paca().
+		 *
+		 * On the read side the barrier is in pte_xchg(), which orders
+		 * the store to the PTE vs the load of mm_cpumask.
+		 */
+		smp_mb();
+	}
+
 	/* 32-bit keeps track of the current PGDIR in the thread struct */
 #ifdef CONFIG_PPC32
 	tsk->thread.pgdir = next->pgd;

build/linux/arch/powerpc/include/asm/pgtable-be-types.h

@@ -87,6 +87,7 @@ static inline bool pte_xchg(pte_t *ptep, pte_t old, pte_t new)
 	unsigned long *p = (unsigned long *)ptep;
 	__be64 prev;
 
+	/* See comment in switch_mm_irqs_off() */
 	prev = (__force __be64)__cmpxchg_u64(p, (__force unsigned long)pte_raw(old),
 					     (__force unsigned long)pte_raw(new));
 

build/linux/arch/powerpc/include/asm/pgtable-types.h

@@ -62,6 +62,7 @@ static inline bool pte_xchg(pte_t *ptep, pte_t old, pte_t new)
 {
 	unsigned long *p = (unsigned long *)ptep;
 
+	/* See comment in switch_mm_irqs_off() */
 	return pte_val(old) == __cmpxchg_u64(p, pte_val(old), pte_val(new));
 }
 #endif

build/linux/arch/s390/kvm/sthyi.c

@@ -394,7 +394,7 @@ static int sthyi(u64 vaddr)
 		"srl     %[cc],28\n"
 		: [cc] "=d" (cc)
 		: [code] "d" (code), [addr] "a" (addr)
-		: "memory", "cc");
+		: "3", "memory", "cc");
 	return cc;
 }
 
@@ -425,14 +425,17 @@ int handle_sthyi(struct kvm_vcpu *vcpu)
 	VCPU_EVENT(vcpu, 3, "STHYI: fc: %llu addr: 0x%016llx", code, addr);
 	trace_kvm_s390_handle_sthyi(vcpu, code, addr);
 
-	if (reg1 == reg2 || reg1 & 1 || reg2 & 1 || addr & ~PAGE_MASK)
+	if (reg1 == reg2 || reg1 & 1 || reg2 & 1)
 		return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
 
 	if (code & 0xffff) {
 		cc = 3;
 		goto out;
 	}
 
+	if (addr & ~PAGE_MASK)
+		return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+
 	/*
 	 * If the page has not yet been faulted in, we want to do that
 	 * now and not after all the expensive calculations.

build/linux/arch/sparc/kernel/pci_sun4v.c

@@ -1241,8 +1241,6 @@ static int pci_sun4v_probe(struct platform_device *op)
 			 * ATU group, but ATU hcalls won't be available.
 			 */
 			hv_atu = false;
-			pr_err(PFX "Could not register hvapi ATU err=%d\n",
-			       err);
 		} else {
 			pr_info(PFX "Registered hvapi ATU major[%lu] minor[%lu]\n",
 				vatu_major, vatu_minor);

build/linux/arch/x86/include/asm/fpu/internal.h

@@ -450,10 +450,10 @@ static inline int copy_fpregs_to_fpstate(struct fpu *fpu)
 	return 0;
 }
 
-static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate)
+static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate, u64 mask)
 {
 	if (use_xsave()) {
-		copy_kernel_to_xregs(&fpstate->xsave, -1);
+		copy_kernel_to_xregs(&fpstate->xsave, mask);
 	} else {
 		if (use_fxsr())
 			copy_kernel_to_fxregs(&fpstate->fxsave);
@@ -477,7 +477,7 @@ static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate)
 			: : [addr] "m" (fpstate));
 	}
 
-	__copy_kernel_to_fpregs(fpstate);
+	__copy_kernel_to_fpregs(fpstate, -1);
 }
 
 extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size);

build/linux/arch/x86/include/asm/kvm_host.h

@@ -486,6 +486,7 @@ struct kvm_vcpu_arch {
 	unsigned long cr4;
 	unsigned long cr4_guest_owned_bits;
 	unsigned long cr8;
+	u32 pkru;
 	u32 hflags;
 	u64 efer;
 	u64 apic_base;

build/linux/arch/x86/include/asm/mmu_context.h

@@ -116,9 +116,7 @@ static inline int init_new_context(struct task_struct *tsk,
 		mm->context.execute_only_pkey = -1;
 	}
 	#endif
-	init_new_context_ldt(tsk, mm);
-
-	return 0;
+	return init_new_context_ldt(tsk, mm);
 }
 static inline void destroy_context(struct mm_struct *mm)
 {

build/linux/arch/x86/kvm/cpuid.c

@@ -469,7 +469,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 			entry->ecx &= kvm_cpuid_7_0_ecx_x86_features;
 			cpuid_mask(&entry->ecx, CPUID_7_ECX);
 			/* PKU is not yet implemented for shadow paging. */
-			if (!tdp_enabled)
+			if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
 				entry->ecx &= ~F(PKU);
 			entry->edx &= kvm_cpuid_7_0_edx_x86_features;
 			entry->edx &= get_scattered_cpuid_leaf(7, 0, CPUID_EDX);

build/linux/arch/x86/kvm/kvm_cache_regs.h

@@ -84,11 +84,6 @@ static inline u64 kvm_read_edx_eax(struct kvm_vcpu *vcpu)
 		| ((u64)(kvm_register_read(vcpu, VCPU_REGS_RDX) & -1u) << 32);
 }
 
-static inline u32 kvm_read_pkru(struct kvm_vcpu *vcpu)
-{
-	return kvm_x86_ops->get_pkru(vcpu);
-}
-
 static inline void enter_guest_mode(struct kvm_vcpu *vcpu)
 {
 	vcpu->arch.hflags |= HF_GUEST_MASK;

build/linux/arch/x86/kvm/mmu.h

@@ -182,7 +182,7 @@ static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 		* index of the protection domain, so pte_pkey * 2 is
 		* is the index of the first bit for the domain.
 		*/
-		pkru_bits = (kvm_read_pkru(vcpu) >> (pte_pkey * 2)) & 3;
+		pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
 
 		/* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
 		offset = (pfec & ~1) +