Remove unnecessary call to gpiochip_remove #6684
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See: https://forums.raspberrypi.com/viewtopic.php?p=2159344 Signed-off-by: Phil Elwell <[email protected]>
Users have reported log spam created by "Event Ring Full" xHC event TRBs. These are caused by interrupt latency in conjunction with a very busy set of devices on the bus. The errors are benign, but throughput will suffer as the xHC will pause processing of transfers until the event ring is drained by the kernel. Expand the number of event TRB slots available by increasing the number of event ring segments in the ERST. Controllers have a hardware-defined limit as to the number of ERST entries they can process, so make the actual number in use min(ERST_MAX_SEGS, hw_max). Signed-off-by: Jonathan Bell <[email protected]>
Step wise governor increases the mitigation level when the temperature goes above a threshold and will decrease the mitigation when the temperature falls below the threshold. If it were a case, where the temperature hovers around a threshold, the mitigation will be applied and removed at every iteration. This reaction to the temperature is inefficient for performance. The use of hysteresis temperature could avoid this ping-pong of mitigation by relaxing the mitigation to happen only when the temperature goes below this lower hysteresis value. Signed-off-by: Ram Chandrasekar <[email protected]> Signed-off-by: Lina Iyer <[email protected]> drivers: thermal: step_wise: avoid throttling at hysteresis temperature after dropping below it Signed-off-by: Serge Schneider <[email protected]> Fix hysteresis support in gov_step_wise.c Directly get hyst value instead of going through an optional and, now, unimplemented function. Signed-off-by: Jürgen Kreileder <[email protected]>
The mainline driver has implemented analogue gain using the control V4L2_CID_GAIN instead of V4L2_CID_ANALOGUE_GAIN. libcamera requires V4L2_CID_ANALOGUE_GAIN, and therefore fails. Update the driver to use V4L2_CID_ANALOGUE_GAIN. Signed-off-by: Dave Stevenson <[email protected]>
Commit 7cd7065 ("drm/bridge: display-connector: implement bus fmts callbacks") added use of drm_atomic_helper_bridge_* functions, but didn't select the dependency of DRM_KMS_HELPER. If nothing else selected that dependency it resulted in a build failure. Select the missing dependency. Fixes: 7cd7065 ("drm/bridge: display-connector: implement bus fmts callbacks") Signed-off-by: Dave Stevenson <[email protected]>
Add YAML device tree bindings for the ROHM BU64754 VCM Motor Driver for Camera Autofocus. Signed-off-by: Kieran Bingham <[email protected]> Signed-off-by: Jacopo Mondi <[email protected]>
Add support for the ROHM BU64754 Motor Driver for Camera Autofocus. A V4L2 Subdevice is registered and provides a single V4L2_CID_FOCUS_ABSOLUTE control. Signed-off-by: Kieran Bingham <[email protected]> Signed-off-by: Jacopo Mondi <[email protected]>
Pi 5 uses BL31 as its armstub file, so the reset goes via PSCI. Parse any "reboot" parameter as a partition number to reboot into. N.B. This code path is only used if reboot mode has been set to warm or soft. Signed-off-by: Phil Elwell <[email protected]>
CSI2 devices are meant to use the 1Xnn formats rather than 2Xnn such as MEDIA_BUS_FMT_UYVY8_2X8. For devices with ADV7180_FLAG_MIPI_CSI2 set, use MEDIA_BUS_FMT_UYVY8_1X16. Signed-off-by: Dave Stevenson <[email protected]>
For CSI2 receivers that need to know the link frequency, add it as a control to the driver. Interlaced modes are 216Mbp/s or 108MHz, whilst going through the I2P to deinterlace gives 432Mb/s or 216MHz. Signed-off-by: Dave Stevenson <[email protected]>
The forced conversion of native CS lines into software CS lines is done whether or not the controller has been given any CS lines to use. This breaks the use of the spi0-0cs overlay to prevent SPI from claiming any CS lines, particularly with spidev which doesn't pass in the SPI_NO_CS flag at creation. Use the presence of an empty cs-gpios property as an indication that no CS lines should be used, bypassing the native CS conversion code. See: raspberrypi#5835 Signed-off-by: Phil Elwell <[email protected]>
There are three disable bits, one for each bus-instance type. Add a quirk to cover the FS/LS type, and update the slightly mangled quirk descriptions in the process. Signed-off-by: Jonathan Bell <[email protected]>
There are three parkmode disable bits, one for each bus instance type. Add FS/LS and parse the quirk out of DT. Also update the slightly mangled quirk descriptions. Signed-off-by: Jonathan Bell <[email protected]>
Calculate the HCNT and LCNT values for all modes using the rise and fall times of SCL, the aim being a 50/50 mark/space ratio. Signed-off-by: Phil Elwell <[email protected]>
Add support for non-standard bus speeds by treating them as detuned versions of the slowest standard speed not less than the requested speed. Signed-off-by: Phil Elwell <[email protected]>
There are multiple causes of interrupts, errors being one, and only the receipt of data warrants continued polling. See: raspberrypi#2676 Signed-off-by: Phil Elwell <[email protected]>
If enabled, DMA_BOUNCE_UNALIGNED_KMALLOC causes the swiotlb buffers (64MB, by default) to be allocated, even on systems where the DMA controller can reach all of RAM. This is a huge amount of RAM to waste on a device with only 512MB to start with, such as the Zero 2 W. See: raspberrypi#5975 Signed-off-by: Phil Elwell <[email protected]>
This patch adds the device ID for the BCM4343A2 module, found e.g. in the Infineon (Cypress) CYW43439 chip. The required firmware file is named 'BCM4343A2.hcd'. Signed-off-by: Phil Elwell <[email protected]>
PLL_AUDIO has a ternary divider (a copy of the secondary divider) and PLL_VIDEO has a primary phased output. Signed-off-by: Jonathan Bell <[email protected]>
The newer Raspberry Pi 5" and 7" panels have a slightly different register map to the original one. Add a new driver for this regulator. Signed-off-by: Dave Stevenson <[email protected]>
i2c_mux_add_adapter takes a force_nr parameter that allows an explicit bus number to be associated with a channel. However, only i2c-mux-reg and i2c-mux-gpio make use of it. To help with situations where it is desirable to have a fixed, known base address for the channels of a mux, create a "base-nr" property. When force_nr is 0 and base-nr is set and non-zero, form a force_nr value from the sum of base-nr and the channel ID. Signed-off-by: Phil Elwell <[email protected]>
In deep sleep mode (DS1) ARM is off and once exit trigger comes than mailbox Interrupt comes to host and whole reinitiation should be done in the ARM to start TX/RX. Also fix below issus for DS1 exit: 1. Sent Tx Control frame only after firmware redownload complete (check F2 Ready before sending Tx Control frame to Firmware) 2. intermittent High DS1 TX Exit latency time (almost 3sec) ==> This is fixed by skipping host Mailbox interrupt Multiple times (ulp state mechanism) 3. RX GlOM save/restore in Firmware 4. Add ULP event enable & event_msgs_ext iovar configuration in FMAC 5. Add ULP_EVENT_RECV state machine for sbwad support 6. Support 2 Byte Shared memory read for DS1 Exit HUDI implementation Signed-off-by: Praveen Babu C <[email protected]> Signed-off-by: Naveen Gupta <[email protected]> [Merge from 4.14.77 to 5.4.18; set BRCMF_SDIO_MAX_ACCESS_ERRORS to 20] Signed-off-by: Chi-hsien Lin <[email protected]> JIRA: SWWLAN-135583 JIRA: SWWLAN-136577
1. If firmware supports 4-way handshake offload but not supports DPP 4-way offload, when user first connects encryption network, driver will set "sup_wpa 1" to firmware, but it will further result in DPP connection failure since firmware won't send EAPOL frame to host. 2. Fix DPP AP mode handling action frames. 3. For some firmware without fwsup support, the join procedure will be skipped due to "sup_wpa" iovar returning not-support. Check the fwsup feature before do such iovar. Signed-off-by: Kurt Lee <[email protected]> Signed-off-by: Double Lo <[email protected]> Signed-off-by: Chi-hsien Lin <[email protected]>
Firmware has SME functionality but would like the userspace to handle SAE authentication. This patch adds support for such an external SAE authentication mechanism in station mode. Signed-off-by: Chung-Hsien Hsu <[email protected]> Signed-off-by: Chi-hsien Lin <[email protected]>
Commit 7d239fb broke 802.1X authentication by setting profile->use_fwsup = NONE whenever PSK is not used. However 802.1X does not use PSK and requires profile->use_fwsup set to 1X, or brcmf_cfg80211_set_pmk() fails. Fix this by checking that profile->use_fwsup is not already set to 1X and avoid setting it to NONE in that case. Fixes: 7d239fb (brcmfmac: Fix interoperating DPP and other encryption network access) Fixes: raspberrypi#5964
Application class A2 cards require CQ to be enabled to realise their stated performance figures. Add support to enable/disable card CQ via the Performance Enhancement extension register, and cater for the slight differences in command set versus eMMC. Signed-off-by: Jonathan Bell <[email protected]>
The Performance Extension register is regularly accessed in a hot path to do write cache flushes. Don't invoke kmalloc/kfree for every access, preallocate a 512B buffer for this purpose. Also remove an unused alloc in sd_enable_cache(). Signed-off-by: Jonathan Bell <[email protected]>
Add a LED_FULL trigger equivalent to mmc_start_request() in mmc_cqe_start_req(), otherwise it stays off forever. Signed-off-by: Jonathan Bell <[email protected]>
For unknown reasons the controller seems to reset the idle polling timer interval on CQE enable/disable to 8 clocks which is extremely short. Just use the reset value in the eMMC spec (4096 clock periods which at 200MHz is ~20uS). Signed-off-by: Jonathan Bell <[email protected]>
About to add the upstream PCIe nodes, so remove the downstream ones to avoid duplicated nodes and build breakage. Signed-off-by: Dave Stevenson <[email protected]>
Adds DT bindings for bcm2712 MSI-X interrupt peripheral controller. Signed-off-by: Stanimir Varbanov <[email protected]>
Update brcmstb PCIe controller bindings with bcm2712 compatible. Signed-off-by: Stanimir Varbanov <[email protected]>
Add an interrupt controller driver for MSI-X Interrupt Peripheral (MIP) hardware block found in bcm2712. The interrupt controller is used to handle MSI-X interrupts from peripherials behind PCIe endpoints like RP1 south bridge found in RPi5. There are two MIPs on bcm2712, the first has 64 consecutive SPIs assigned to 64 output vectors, and the second has 17 SPIs, but only 8 of them are consecutive starting at the 8th output vector. Signed-off-by: Stanimir Varbanov <[email protected]>
Instead of copying fields from pcie_cfg_data structure to brcm_pcie reference it directly. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelil <[email protected]>
BCM2712 memory map can support up to 64GB of system memory, thus expand the inbound window size in calculation helper function. The change is save for the currently supported SoCs that has smaller inbound window sizes. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]>
Add bare minimum amount of changes in order to support PCIe RC hardware IP found on RPi5. The PCIe controller on bcm2712 is based on bcm7712 and as such it inherits register offsets, perst, bridge_reset ops and inbound windows count. Although, the implementation for bcm2712 needs a workaround related to the control of the bridge_reset where turning off of the root port must not shutdown the bridge_reset and this must be avoided. To implement this workaround a quirks field is introduced in pcie_cfg_data struct. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]>
The default input reference clock for the PHY PLL is 100Mhz, except for some devices where it is 54Mhz like bcm2712C1 and bcm2712D0. To implement this adjustments introduce a new .post_setup op in pcie_cfg_data and call it at the end of brcm_pcie_setup function. The bcm2712 .post_setup callback implements the required MDIO writes that switch the PLL refclk and also change PHY PM clock period. Without this RPi5 PCIex1 is unable to enumerate endpoint devices on the expansion connector. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]>
In case brcmstb PCIe driver and MIP MSI-X interrupt controller drivers are built as modules there could be a race in probing. To avoid this add a softdep to MIP driver to guarantee that MIP driver will be load first. Signed-off-by: Stanimir Varbanov <[email protected]>
A call to of_parse_phandle() increments refcount, of_node_put must be called when done the work on it. Fix missing of_node_put() on the msi_np device node by using scope based of_node_put() cleanups. Cc: [email protected] # v5.10+ Fixes: 40ca1bf ("PCI: brcmstb: Add MSI support") Signed-off-by: Stanimir Varbanov <[email protected]>
Add PCIe devicetree nodes, plus needed reset and mip MSI-X controllers. Signed-off-by: Stanimir Varbanov <[email protected]>
Enable pcie1 and pcie2 DT nodes. Pcie1 is used for the extension connector and pcie2 is used for RP1 south-bridge. Signed-off-by: Stanimir Varbanov <[email protected]>
Make changes to the code that limits the PCIe max speed.
(1) Do the changes before link-up, not after. We do not want
to temporarily rise to a higher speed than desired.
(2) Use constants from pci_reg.h when possible
(3) Use uXX_replace_bits(...) for setting a register field.
(4) Use the internal link capabilities register for writing
the max speed, not the official config space register
where the speed field is RO. Updating this field is
not necessary to limit the speed so this mistake was
harmless.
Signed-off-by: Jim Quinlan <[email protected]>
If regulator_bulk_get() returns an error, no regulators are created and we need to set their number to zero. If we do not do this and the PCIe link-up fails, regulator_bulk_free() will be invoked and effect a panic. Also print out the error value, as we cannot return an error upwards as Linux will WARN on an error from add_bus(). Fixes: 9e6be01 ("PCI: brcmstb: Enable child bus device regulators from DT") Signed-off-by: Jim Quinlan <[email protected]>
Our system for enabling and disabling regulators is designed to work only on the port driver below the root complex. The conditions to discriminate for this case should be the same when we are adding or removing the bus. Without this change the regulators may be disabled prematurely when a bus further down the tree is removed. Fixes: 9e6be01 ("PCI: brcmstb: Enable child bus device regulators from DT") Signed-off-by: Jim Quinlan <[email protected]>
The constants EXT_CFG_DATA and EXT_CFG_INDEX vary by SOC. One of the map_bus methods used these constants, the other used different constants. Fortunately there was no problem because the SoCs that used the latter map_bus method all had the same register constants. Remove the redundant constants and adjust the code to use them. In addition, update EXT_CFG_DATA to use the 4k-page based config space access system, which is what the second map_bus method was already using. Signed-off-by: Jim Quinlan <[email protected]>
The HW team has decided to "tighten" some field definitions in the MDIO packet format. Fortunately these two changes may be made in a backwards compatible manner. The CMD field used to be 12 bits and now is one. This change is backwards compatible because the field's starting bit position is unchanged and the only commands we've used have values 0 and 1. The PORT field's width has been changed from four to five bits. When written, the new bit is not contiguous with the other four. Fortunately, this change is backwards compatible because we have never used anything other than 0 for the port field's value. Signed-off-by: Jim Quinlan <[email protected]>
Just make it clear to the reader that there is a conversion happening, in this case from an int type to an irq_hw_number_t, an unsigned long int. Signed-off-by: Jim Quinlan <[email protected]>
Without this, a default of 0 is used which is very suboptimal for timely service. Consistency with Pi 5 is desired. Signed-off-by: Jonathan Bell <[email protected]>
Allows the usage of ADC8x stacked on top of the DAC8x. Activates all I2S pins and uses now the dummy-dai instead of the formerly used pcm5102 to allow the use of a capture device, too. The simple card driver will probe for the ADC8x and may activate the 8 channel capture. Uses GPIO5 for detection. Signed-off-by: j-schambacher <[email protected]>
The driver probes for the ADC8x which can be stacked on top of the DAC8x. It enables a symmetric 8 channel capture using the dummy-dai. Signed-off-by: j-schambacher <[email protected]>
… imx290" This reverts commit 1180b49.
Add pmkid parameter in "brcmf_auth_req_status_le" structure to align the buffer size defined in firmware "wl_auth_req_status" structure. Link: raspberrypi#6130 Signed-off-by: Ting-Ying Li <[email protected]> Signed-off-by: Phil Elwell <[email protected]>
It was noted that if PV1 was in use to drive DSI1, then the writeback connector could not be used as HVS channel 2 was already in use. The HVS allows PV1 (HVS output 2) to be driven by any HVS channel via the DSP3_MUX setting, but that was hardcoded to be either 2 (for PV1) or disabled for TXP. Expand the available channels field for PV1, and configure DSP3_MUX accordingly. Signed-off-by: Dave Stevenson <[email protected]>
The tests on vc4 (BCM2835-7) were checking for DSI1 muxing being to restricted channel 2, and therefore muxing with TXP was impossible. As we no longer have that restriction, update the capabilities defined for DSI1, move the tests that used to be impossible to the valid list, and extend for additional combinations that are now possible. Signed-off-by: Dave Stevenson <[email protected]>
See: raspberrypi#6497 Signed-off-by: Phil Elwell <[email protected]>
No gpio_chip has been added (registered ) with the core at this point. Calling gpio_chip is therefore not necessary
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I agree with your patch, but this is a problem that exists in the upstream kernel: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pinctrl/bcm/pinctrl-bcm2835.c?h=v6.14-rc4#n1351 You should send it to the upstream maintainers: |
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It'll also want a as it's been wrong since 5.16 so needs backporting to stable. There is also a For curiosity, have you observed this error path being taken in reality, or just noticed it in code review? |
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No gpio_chip has been added (registered ) with the core at this point. Calling gpiochip_remove is therefore not necessary