RP1 DPI: interlaced HSync/VSync alignment (6.12) #6695
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njhollinghurst
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Instead of trying to minimize the delay between seeing HSYNC edge and asserting VSYNC, try to predict the next HSYNC edge precisely. This eliminates the round-trip delay but introduces mode-dependent rounding error. HSYNC->VSYNC lag reduced from ~30ns to -5ns..+10ns (plus up to 5ns synchronization jitter as before). This may benefit e.g. SCART HATs, particularly those that generate Composite Sync using a XNOR gate. Signed-off-by: Nick Hollinghurst <[email protected]>
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Instead of trying to minimize the HSync -> VSync lag, count cycles to predict the next HSync.
It reduces the HSync->VSync offset from about (+30ns .. +35ns), to about (-5ns .. +10ns). There is some mode-dependent rounding error, but for a given video mode the jitter is ~5ns as before.
This is mainly for the benefit of SCART Hats, particularly those that use an XNOR gate to generate Composite Sync, which otherwise could produce glitchier output when used in an interlaced mode with Raspberry Pi 5.
A fringe benefit is that 6 PIO instructions are now free (enough for some RGB LEDs but not for PWM...)