cxgbe(4): add support for stateless offloads for VXLAN traffic.

Hardware assistance includes checksumming (tx and rx), TSO, and RSS on the inner traffic in a VXLAN tunnel. Relnotes: Yes Sponsored by: Chelsio Communications
rcbchan · Sep 18, 2020 · a4a4ad2 · a4a4ad2
1 parent b092fd6
commit a4a4ad2
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diff --git a/share/man/man4/cxgbe.4 b/share/man/man4/cxgbe.4
@@ -31,7 +31,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd Dec 10, 2019
+.Dd September 17, 2020
 .Dt CXGBE 4
 .Os
 .Sh NAME
@@ -61,8 +61,8 @@ driver provides support for PCI Express Ethernet adapters based on
 the Chelsio Terminator 4, Terminator 5, and Terminator 6 ASICs (T4, T5, and T6).
 The driver supports Jumbo Frames, Transmit/Receive checksum offload,
 TCP segmentation offload (TSO), Large Receive Offload (LRO), VLAN
-tag insertion/extraction, VLAN checksum offload, VLAN TSO, and
-Receive Side Steering (RSS).
+tag insertion/extraction, VLAN checksum offload, VLAN TSO, VXLAN checksum
+offload, VXLAN TSO, and Receive Side Steering (RSS).
 For further hardware information and questions related to hardware
 requirements, see
 .Pa http://www.chelsio.com/ .

diff --git a/sys/dev/cxgbe/adapter.h b/sys/dev/cxgbe/adapter.h
@@ -119,6 +119,7 @@ enum {
 	TX_SGL_SEGS = 39,
 	TX_SGL_SEGS_TSO = 38,
 	TX_SGL_SEGS_EO_TSO = 30,	/* XXX: lower for IPv6. */
+	TX_SGL_SEGS_VXLAN_TSO = 37,
 	TX_WR_FLITS = SGE_MAX_WR_LEN / 8
 };
 
@@ -286,6 +287,7 @@ struct port_info {
 	int nvi;
 	int up_vis;
 	int uld_vis;
+	bool vxlan_tcam_entry;
 
 	struct tx_sched_params *sched_params;
 
@@ -593,6 +595,8 @@ struct sge_txq {
 	uint64_t txpkts0_pkts;	/* # of frames in type0 coalesced tx WRs */
 	uint64_t txpkts1_pkts;	/* # of frames in type1 coalesced tx WRs */
 	uint64_t raw_wrs;	/* # of raw work requests (alloc_wr_mbuf) */
+	uint64_t vxlan_tso_wrs;	/* # of VXLAN TSO work requests */
+	uint64_t vxlan_txcsum;
 
 	uint64_t kern_tls_records;
 	uint64_t kern_tls_short;
@@ -625,6 +629,7 @@ struct sge_rxq {
 
 	uint64_t rxcsum;	/* # of times hardware assisted with checksum */
 	uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
+	uint64_t vxlan_rxcsum;
 
 	/* stats for not-that-common events */
 
@@ -848,6 +853,11 @@ struct adapter {
 	int lro_timeout;
 	int sc_do_rxcopy;
 
+	int vxlan_port;
+	u_int vxlan_refcount;
+	int rawf_base;
+	int nrawf;
+
 	struct taskqueue *tq[MAX_NCHAN];	/* General purpose taskqueues */
 	struct task async_event_task;
 	struct port_info *port[MAX_NPORTS];

diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h
@@ -249,7 +249,7 @@ struct tp_params {
 	uint32_t max_rx_pdu;
 	uint32_t max_tx_pdu;
 	uint64_t hash_filter_mask;
-	__be16 err_vec_mask;
+	bool rx_pkt_encap;
 
 	int8_t fcoe_shift;
 	int8_t port_shift;

diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
@@ -9647,19 +9647,11 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
 
 	read_filter_mode_and_ingress_config(adap, sleep_ok);
 
-	/*
-	 * Cache a mask of the bits that represent the error vector portion of
-	 * rx_pkt.err_vec.  T6+ can use a compressed error vector to make room
-	 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE).
-	 */
-	tpp->err_vec_mask = htobe16(0xffff);
 	if (chip_id(adap) > CHELSIO_T5) {
 		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
-		if (v & F_CRXPKTENC) {
-			tpp->err_vec_mask =
-			    htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC));
-		}
-	}
+		tpp->rx_pkt_encap = v & F_CRXPKTENC;
+	} else
+		tpp->rx_pkt_encap = false;
 
 	rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE);
 	tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE);

diff --git a/sys/dev/cxgbe/firmware/t6fw_cfg.txt b/sys/dev/cxgbe/firmware/t6fw_cfg.txt
@@ -146,7 +146,8 @@
 	nethctrl = 1024
 	neq = 2048
 	nqpcq = 8192
-	nexactf = 456
+	nexactf = 454
+	nrawf = 2
 	cmask = all
 	pmask = all
 	ncrypto_lookaside = 16
@@ -272,7 +273,7 @@
 
 [fini]
 	version = 0x1
-	checksum = 0x13640470
+	checksum = 0xa92352a8
 #
 # $FreeBSD$
 #