Repository containing the guide and code for booting RISC-V full system linux using gem5.

A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V Cores, SoC platforms and SoCs

A simple superscalar out-of-order RISC-V microprocessor

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

SonicBOOM: The Berkeley Out-of-Order Machine

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases

Common SystemVerilog components

Various HDL (Verilog) IP Cores

EE 260 Winter 2017: Advanced VLSI Design

A DDR3 memory controller in Verilog for various FPGAs

The main Embench repository

FPGA Projects Done For the University Class - Verilog

VHDL Codes for my first internship on GSTL

Modular hardware build system

Creating beautiful gem5 simulations

The official repository for the gem5 computer-system architecture simulator.

A documentation on my findings in Cadence

FPGA250 aboard the eFabless Caravel

Полезные ресурсы по тематике FPGA / ПЛИС

Repository for Hornet RISC-V Core

RARS -- RISC-V Assembler and Runtime Simulator