StoreQueue: re-enter exceptionbuffer when store_s2

storeunit will resp some exception (misaligned or pagefault) when store_s1,
however, pmp will raise access fault when store_s2, which should be written into exceptionbuffer

src/main/scala/xiangshan/mem/MemCommon.scala

@@ -90,6 +90,7 @@ class LsPipelineBundle(implicit p: Parameters) extends XSBundle
   val miss = Bool()
   val tlbMiss = Bool()
   val ptwBack = Bool()
+  val af = Bool()
   val mmio = Bool()
   val atomic = Bool()
   val rsIdx = UInt(log2Up(MemIQSizeMax).W)
@@ -163,6 +164,7 @@ class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle {
     if (latch) miss := RegNext(input.miss) else miss := input.miss
     if (latch) tlbMiss := RegNext(input.tlbMiss) else tlbMiss := input.tlbMiss
     if (latch) ptwBack := RegNext(input.ptwBack) else ptwBack := input.ptwBack
+    if (latch) af := RegNext(input.af) else af := input.af
     if (latch) mmio := RegNext(input.mmio) else mmio := input.mmio
     if (latch) rsIdx := RegNext(input.rsIdx) else rsIdx := input.rsIdx
     if (latch) forwardMask := RegNext(input.forwardMask) else forwardMask := input.forwardMask

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -32,6 +32,7 @@ import xiangshan.backend.Bundles.{DynInst, MemExuOutput}
 import xiangshan.backend.decode.isa.bitfield.{Riscv32BitInst, XSInstBitFields}
 import xiangshan.backend.fu.FuConfig._
 import xiangshan.backend.fu.FuType
+import xiangshan.ExceptionNO._
 
 class SqPtr(implicit p: Parameters) extends CircularQueuePtr[SqPtr](
   p => p(XSCoreParamsKey).StoreQueueSize
@@ -69,7 +70,7 @@ class DataBufferEntry (implicit p: Parameters)  extends DCacheBundle {
 class StoreExceptionBuffer(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper {
   val io = IO(new Bundle() {
     val redirect = Flipped(ValidIO(new Redirect))
-    val storeAddrIn = Vec(StorePipelineWidth + VecStorePipelineWidth, Flipped(ValidIO(new LsPipelineBundle())))
+    val storeAddrIn = Vec(StorePipelineWidth * 2 + VecStorePipelineWidth, Flipped(ValidIO(new LsPipelineBundle())))
     val exceptionAddr = new ExceptionAddrIO
   })
 
@@ -83,15 +84,15 @@ class StoreExceptionBuffer(implicit p: Parameters) extends XSModule with HasCirc
 
   // S2: delay 1 cycle
   val s2_req = RegNext(s1_req)
-  val s2_valid = (0 until StorePipelineWidth + VecStorePipelineWidth).map(i =>
+  val s2_valid = (0 until StorePipelineWidth * 2 + VecStorePipelineWidth).map(i =>
     RegNext(s1_valid(i)) &&
       !s2_req(i).uop.robIdx.needFlush(RegNext(io.redirect)) &&
       !s2_req(i).uop.robIdx.needFlush(io.redirect)
   )
   val s2_has_exception = s2_req.map(x => ExceptionNO.selectByFu(x.uop.exceptionVec, StaCfg).asUInt.orR)
 
-  val s2_enqueue = Wire(Vec(StorePipelineWidth + VecStorePipelineWidth, Bool()))
-  for (w <- 0 until StorePipelineWidth + VecStorePipelineWidth) {
+  val s2_enqueue = Wire(Vec(StorePipelineWidth * 2 + VecStorePipelineWidth, Bool()))
+  for (w <- 0 until StorePipelineWidth * 2 + VecStorePipelineWidth) {
     s2_enqueue(w) := s2_valid(w) && s2_has_exception(w)
   }
 
@@ -214,14 +215,14 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   exceptionBuffer.io.exceptionAddr.isStore := DontCare
   // vlsu exception!
   for (i <- 0 until VecStorePipelineWidth) {
-    exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).valid               := io.vecFeedback(i).valid && io.vecFeedback(i).bits.feedback(VecFeedbacks.FLUSH) // have exception
-    exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).bits                := DontCare
-    exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).bits.vaddr          := io.vecFeedback(i).bits.vaddr
-    exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).bits.uop.uopIdx     := io.vecFeedback(i).bits.uopidx
-    exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).bits.uop.robIdx     := io.vecFeedback(i).bits.robidx
-    exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).bits.uop.vpu.vstart := io.vecFeedback(i).bits.vstart
-    exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).bits.uop.vpu.vl     := io.vecFeedback(i).bits.vl
-    exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).bits.uop.exceptionVec     := io.vecFeedback(i).bits.exceptionVec
+    exceptionBuffer.io.storeAddrIn(StorePipelineWidth * 2 + i).valid               := io.vecFeedback(i).valid && io.vecFeedback(i).bits.feedback(VecFeedbacks.FLUSH) // have exception
+    exceptionBuffer.io.storeAddrIn(StorePipelineWidth * 2 + i).bits                := DontCare
+    exceptionBuffer.io.storeAddrIn(StorePipelineWidth * 2 + i).bits.vaddr          := io.vecFeedback(i).bits.vaddr
+    exceptionBuffer.io.storeAddrIn(StorePipelineWidth * 2 + i).bits.uop.uopIdx     := io.vecFeedback(i).bits.uopidx
+    exceptionBuffer.io.storeAddrIn(StorePipelineWidth * 2 + i).bits.uop.robIdx     := io.vecFeedback(i).bits.robidx
+    exceptionBuffer.io.storeAddrIn(StorePipelineWidth * 2 + i).bits.uop.vpu.vstart := io.vecFeedback(i).bits.vstart
+    exceptionBuffer.io.storeAddrIn(StorePipelineWidth * 2 + i).bits.uop.vpu.vl     := io.vecFeedback(i).bits.vl
+    exceptionBuffer.io.storeAddrIn(StorePipelineWidth * 2 + i).bits.uop.exceptionVec     := io.vecFeedback(i).bits.exceptionVec
   }
 
 
@@ -430,6 +431,9 @@ class StoreQueue(implicit p: Parameters) extends XSModule
     val stWbIndex = io.storeAddrIn(i).bits.uop.sqIdx.value
     exceptionBuffer.io.storeAddrIn(i).valid := io.storeAddrIn(i).fire && !io.storeAddrIn(i).bits.miss && !io.storeAddrIn(i).bits.isvec
     exceptionBuffer.io.storeAddrIn(i).bits := io.storeAddrIn(i).bits
+    // will re-enter exceptionbuffer at store_s2
+    exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).valid := false.B
+    exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).bits := 0.U.asTypeOf(new LsPipelineBundle)
 
     when (io.storeAddrIn(i).fire) {
       val addr_valid = !io.storeAddrIn(i).bits.miss
@@ -481,6 +485,12 @@ class StoreQueue(implicit p: Parameters) extends XSModule
     when (storeAddrInFireReg) {
       prefetch(stWbIndexReg) := io.storeAddrInRe(i).miss
     }
+    // enter exceptionbuffer again
+    when (storeAddrInFireReg) {
+      exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).valid := io.storeAddrInRe(i).af
+      exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).bits := RegEnable(io.storeAddrIn(i).bits, io.storeAddrIn(i).fire && !io.storeAddrIn(i).bits.miss)
+      exceptionBuffer.io.storeAddrIn(StorePipelineWidth + i).bits.uop.exceptionVec(storeAccessFault) := io.storeAddrInRe(i).af
+    }
 
     when(vaddrModule.io.wen(i)){
       debug_vaddr(vaddrModule.io.waddr(i)) := vaddrModule.io.wdata(i)

src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

@@ -312,6 +312,7 @@ class StoreUnit(implicit p: Parameters) extends XSModule
   s2_kill := ((s2_mmio && !s2_exception) && !s2_in.isvec) || s2_in.uop.robIdx.needFlush(io.redirect)
 
   s2_out        := s2_in
+  s2_out.af     := s2_pmp.st && !s2_in.isvec
   s2_out.mmio   := s2_mmio && !s2_exception
   s2_out.atomic := s2_in.atomic || s2_pmp.atomic
   s2_out.uop.exceptionVec(storeAccessFault) := (s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st) && s2_vecActive